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([2a01:e0a:59e:9d80:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id k22-20020a05600c0b5600b003fe601a7d46sm18368605wmr.45.2023.09.26.08.39.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 26 Sep 2023 08:39:13 -0700 (PDT) Message-ID: Date: Tue, 26 Sep 2023 17:39:12 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Subject: Re: [PATCH 3/3] hw/arm/smmuv3: Advertise SMMUv3.1-XNX feature Content-Language: en-US To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Mostafa Saleh References: <20230914145705.1648377-1-peter.maydell@linaro.org> <20230914145705.1648377-4-peter.maydell@linaro.org> From: Eric Auger In-Reply-To: <20230914145705.1648377-4-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -35 X-Spam_score: -3.6 X-Spam_bar: --- X-Spam_report: (-3.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.473, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Peter, On 9/14/23 16:57, Peter Maydell wrote: > The SMMUv3.1-XNX feature is mandatory for an SMMUv3.1 if S2P is > supported, so we should theoretically have implemented it as part of > the recent S2P work. Fortunately, for us the implementation is a > no-op. > > This feature is about interpretation of the stage 2 page table > descriptor XN bits, which control execute permissions. > > For QEMU, the permission bits passed to an IOMMU (via MemTxAttrs and > IOMMUAccessFlags) only indicate read and write; we do not distinguish > data reads from instruction reads outside the CPU proper. In the > SMMU architecture's terms, our interconnect between the client device > and the SMMU doesn't have the ability to convey the INST attribute, > and we therefore use the default value of "data" for this attribute. > > We also do not support the bits in the Stream Table Entry that can > override the on-the-bus transaction attribute permissions (we do not > set SMMU_IDR1.ATTR_PERMS_OVR=1). you may precise it is called INSTCFG > > These two things together mean that for our implementation, it never > has to deal with transactions with the INST attribute, and so it can > correctly ignore the XN bits entirely. So we already implement > FEAT_XNX's "XN field is now 2 bits, not 1" behaviour to the extent > that we need to. > > Advertise the presence of the feature in SMMU_IDR3.XNX. > > Signed-off-by: Peter Maydell > --- > hw/arm/smmuv3.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c > index 94d388fc950..d9e639f7c41 100644 > --- a/hw/arm/smmuv3.c > +++ b/hw/arm/smmuv3.c > @@ -279,6 +279,7 @@ static void smmuv3_init_regs(SMMUv3State *s) > s->idr[1] = FIELD_DP32(s->idr[1], IDR1, CMDQS, SMMU_CMDQS); > > s->idr[3] = FIELD_DP32(s->idr[3], IDR3, HAD, 1); > + s->idr[3] = FIELD_DP32(s->idr[3], IDR3, XNX, 1); > s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL, 1); > s->idr[3] = FIELD_DP32(s->idr[3], IDR3, BBML, 2); > With Mostafa's suggestion Reviewed-by: Eric Auger Thanks Eric