From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49398) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZBsi4-0001f5-Lv for qemu-devel@nongnu.org; Sun, 05 Jul 2015 18:48:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZBsi0-0002Xh-SK for qemu-devel@nongnu.org; Sun, 05 Jul 2015 18:48:28 -0400 Received: from mail-la0-x22c.google.com ([2a00:1450:4010:c03::22c]:36335) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZBsi0-0002WS-LY for qemu-devel@nongnu.org; Sun, 05 Jul 2015 18:48:24 -0400 Received: by lagc2 with SMTP id c2so134519819lag.3 for ; Sun, 05 Jul 2015 15:48:23 -0700 (PDT) From: Dmitry Osipenko Date: Mon, 6 Jul 2015 01:47:48 +0300 Message-Id: In-Reply-To: References: In-Reply-To: References: Subject: [Qemu-devel] [PATCH v3 2/2] arm_mptimer: Respect IT bit state List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Crosthwaite , Peter Maydell Cc: Paolo Bonzini , QEMU Developers The timer should fire interrupt only if IT(interrupt enable) bit state of control register is enabled and the timer should update IRQ status on IT bit change as it would mask/unmask the interrupt line. Signed-off-by: Dmitry Osipenko Reviewed-by: Peter Crosthwaite --- v2: Added missed IRQ status update on control register write as per Peter Crosthwaite comment. v3: No code change, just re-send. hw/timer/arm_mptimer.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/hw/timer/arm_mptimer.c b/hw/timer/arm_mptimer.c index 0e132b1..22fa46e 100644 --- a/hw/timer/arm_mptimer.c +++ b/hw/timer/arm_mptimer.c @@ -38,7 +38,7 @@ static inline int get_current_cpu(ARMMPTimerState *s) static inline void timerblock_update_irq(TimerBlock *tb) { - qemu_set_irq(tb->irq, tb->status); + qemu_set_irq(tb->irq, tb->status && (tb->control & 4)); } /* Return conversion factor from mpcore timer ticks to qemu timer ticks. */ @@ -122,6 +122,9 @@ static void timerblock_write(void *opaque, hwaddr addr, case 8: /* Control. */ old = tb->control; tb->control = value; + if ((old & 4) != (value & 4)) { + timerblock_update_irq(tb); + } if (value & 1) { if ((old & 1) && (tb->count != 0)) { /* Do nothing if timer is ticking right now. */ -- 2.4.4