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Wed, 6 Sep 2023 12:12:04 +0000 (GMT) Message-ID: Subject: Re: [PATCH v22 03/20] target/s390x/cpu topology: handle STSI(15) and build the SYSIB From: Nina Schoetterl-Glausch To: Thomas Huth , qemu-devel@nongnu.org, qemu-s390x@nongnu.org, Eduardo Habkost , Marcel Apfelbaum , Paolo Bonzini , Halil Pasic , Christian Borntraeger , Eric Farman , Richard Henderson , David Hildenbrand , Eric Blake , Markus Armbruster , Michael Roth Cc: Philippe =?ISO-8859-1?Q?Mathieu-Daud=E9?= , Yanan Wang , "Daniel P." =?ISO-8859-1?Q?Berrang=E9?= , Ilya Leoshkevich , Cleber Rosa , Wainer dos Santos Moschetta , Beraldo Leal , Pierre Morel Date: Wed, 06 Sep 2023 14:12:03 +0200 In-Reply-To: References: <20230901155812.2696560-1-nsg@linux.ibm.com> <20230901155812.2696560-4-nsg@linux.ibm.com> <4df5a37496ed0a0912926f19406efcce114beaf1.camel@linux.ibm.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.48.4 (3.48.4-1.fc38) MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: tDN69hcVVfFeledqQFkiyRBRbj6S9gOD X-Proofpoint-ORIG-GUID: xT08qfSH8SPo9UGpy5mMwURYt9ajmmsv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-09-06_05,2023-09-05_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 malwarescore=0 clxscore=1015 suspectscore=0 impostorscore=0 spamscore=0 lowpriorityscore=0 adultscore=0 mlxlogscore=999 priorityscore=1501 mlxscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2309060103 Received-SPF: pass client-ip=148.163.158.5; envelope-from=nsg@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, 2023-09-06 at 10:21 +0200, Thomas Huth wrote: > On 05/09/2023 17.25, Nina Schoetterl-Glausch wrote: > > On Tue, 2023-09-05 at 15:26 +0200, Thomas Huth wrote: > > > On 01/09/2023 17.57, Nina Schoetterl-Glausch wrote: > > > > From: Pierre Morel > > > >=20 > > > > On interception of STSI(15.1.x) the System Information Block > > > > (SYSIB) is built from the list of pre-ordered topology entries. > > > >=20 > > > > Signed-off-by: Pierre Morel > > > > Co-developed-by: Nina Schoetterl-Glausch > > > > Signed-off-by: Nina Schoetterl-Glausch > > > > --- > ... > > > > +/** > > > > + * s390_topology_fill_list_sorted: > > > > + * > > > > + * Loop over all CPU and insert it at the right place > > > > + * inside the TLE entry list. > > > > + * Fill the S390Topology list with entries according to the order > > > > + * specified by the PoP. > > > > + */ > > > > +static void s390_topology_fill_list_sorted(S390TopologyList *topol= ogy_list) > > > > +{ > > > > + CPUState *cs; > > > > + S390TopologyEntry sentinel; > > > > + > > > > + QTAILQ_INIT(topology_list); > > > > + > > > > + sentinel.id.id =3D cpu_to_be64(UINT64_MAX); >=20 > Since you don't do swapping for entry->id.id below, why do you do it here= ? Because an integer in cpu endianess is converted to the big endian storage format. So then there is a cpu -> big -> cpu round trip with the comparison below and the value is the max. Of course this is entirely cosmetic, since UINT64_MAX is all ones. > > > > + QTAILQ_INSERT_HEAD(topology_list, &sentinel, next); > > > > + > > > > + CPU_FOREACH(cs) { > > > > + s390_topology_id id =3D s390_topology_from_cpu(S390_CPU(cs= )); > > > > + S390TopologyEntry *entry, *tmp; > > > > + > > > > + QTAILQ_FOREACH(tmp, topology_list, next) { > > > > + if (id.id =3D=3D tmp->id.id) { > > > > + entry =3D tmp; > > > > + break; > >=20 > > I think I'll add a comment here. > >=20 > > /* > > * Earlier bytes have higher order -> big endian. > > * E.g. an entry with higher drawer number should be later in the list= , > > * no matter the later fields (book, socket, etc) > > */ >=20 > Ugh, so this swapping is not due to real endianness issues, but just due = to Yeah. > ordering? ... that's very ugly! I'd prefer to be more verbose and compare= =20 I kinda didn't like the verbosity of it, since I then need to copy paste the whole thing because I also need an equality check. I considered implementing <=3D, then a =3D=3D b as a <=3D b && b <=3D a, wh= ich seems fine on second thought, so I'll do that.=20 And maybe help the compiler by putting __attribute__((pure)) on there. > book by book, drawer by drawer, etc. instread. Or is this function that= =20 > performance critical that we must save every possible CPU cycle here? No. >=20 > Thomas >=20 >=20 > >=20 > > > > + } else if (be64_to_cpu(id.id) < be64_to_cpu(tmp->id.id= )) { > > > > + entry =3D g_malloc0(sizeof(*entry)); > > >=20 > > > Maybe nicer to use g_new0 here instead? > >=20 > > I don't think it makes much of a difference. > >=20 > > >=20 > > > > + entry->id.id =3D id.id; > > >=20 > > > Should this get a cpu_to_be64() ? > >=20 > > No, there is no interpretation of the value here, just a copy. > > >=20 > > > > + QTAILQ_INSERT_BEFORE(tmp, entry, next); > > > > + break; > > > > + } > > > > + } > > > > + s390_topology_add_cpu_to_entry(entry, S390_CPU(cs)); > > > > + } > > > > + > > > > + QTAILQ_REMOVE(topology_list, &sentinel, next); > > > > +} > > >=20 > > > Thomas > > >=20 > > >=20 > >=20 >=20