From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Jiaxun Yang <jiaxun.yang@flygoat.com>, qemu-devel@nongnu.org
Cc: Huacai Chen <chenhuacai@kernel.org>, Song Gao <gaosong@loongson.cn>
Subject: Re: [PATCH 5/5] hw/mips/loongson3_virt: Wire up loongson_ipi device
Date: Mon, 3 Jun 2024 17:46:51 +0200 [thread overview]
Message-ID: <f2e61128-003c-48c9-bab4-20422d195145@linaro.org> (raw)
In-Reply-To: <20240508-loongson3-ipi-v1-5-1a7b67704664@flygoat.com>
On 8/5/24 15:06, Jiaxun Yang wrote:
> Wire up loongson_ipi device for loongson3_virt machine, so we
> can have SMP support for TCG backend as well.
>
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
> hw/mips/Kconfig | 1 +
> hw/mips/loongson3_bootp.c | 2 --
> hw/mips/loongson3_bootp.h | 3 +++
> hw/mips/loongson3_virt.c | 39 +++++++++++++++++++++++++++++++++++++--
> 4 files changed, 41 insertions(+), 4 deletions(-)
> @@ -534,12 +553,28 @@ static void mips_loongson3_virt_init(MachineState *machine)
> cpu_mips_clock_init(cpu);
> qemu_register_reset(main_cpu_reset, cpu);
>
> - if (i >= 4) {
> + if (ipi) {
> + hwaddr base = ((hwaddr)node << 44) + virt_memmap[VIRT_IPI].base;
> + base += core * 0x100;
> + qdev_connect_gpio_out(ipi, i, cpu->env.irq[6]);
> + sysbus_mmio_map(SYS_BUS_DEVICE(ipi), i + 2, base);
> + }
> +
> + if (ase_lcsr_available(&MIPS_CPU(cpu)->env)) {
> + MemoryRegion *core_iocsr = g_new(MemoryRegion, 1);
> + g_autofree char *name = g_strdup_printf("loongson3.core%d_iocsr", i);
> + memory_region_init_alias(core_iocsr, OBJECT(machine), name,
Region owner should be vCPU (core) IMO, not machine. But maybe need
another approach (see my comment on patch #3), although not sure if
easy with KVM.
> + iocsr, 0, UINT32_MAX);
> + memory_region_add_subregion(&MIPS_CPU(cpu)->env.iocsr.mr,
> + 0, core_iocsr);
> + }
> +
> + if (node > 0) {
> continue; /* Only node-0 can be connected to LIOINTC */
> }
>
> for (ip = 0; ip < 4 ; ip++) {
> - int pin = i * 4 + ip;
> + int pin = core * LOONGSON3_CORE_PER_NODE + ip;
> sysbus_connect_irq(SYS_BUS_DEVICE(liointc),
> pin, cpu->env.irq[ip + 2]);
> }
>
next prev parent reply other threads:[~2024-06-03 15:47 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-08 13:06 [PATCH 0/5] hw/mips/loongson3_virt: Implement IPI support Jiaxun Yang
2024-05-08 13:06 ` [PATCH 1/5] hw/intc/loongarch_ipi: Remove pointless MAX_CPU check Jiaxun Yang
2024-05-08 16:22 ` Philippe Mathieu-Daudé
2024-05-08 13:06 ` [PATCH 2/5] hw/intc/loongarch_ipi: Rename as loongson_ipi Jiaxun Yang
2024-05-08 16:24 ` Philippe Mathieu-Daudé
2024-05-08 13:06 ` [PATCH 3/5] hw/intc/loongson_ipi: Implement IOCSR address space for MIPS Jiaxun Yang
2024-05-08 16:21 ` Philippe Mathieu-Daudé
2024-06-03 15:45 ` Philippe Mathieu-Daudé
2024-06-04 10:35 ` Jiaxun Yang
2024-06-04 12:37 ` gaosong
2024-05-08 13:06 ` [PATCH 4/5] hw/intc/loongson_ipi: Provide per core MMIO address spaces Jiaxun Yang
2024-05-08 13:06 ` [PATCH 5/5] hw/mips/loongson3_virt: Wire up loongson_ipi device Jiaxun Yang
2024-06-03 15:46 ` Philippe Mathieu-Daudé [this message]
2024-05-08 21:41 ` [PATCH 0/5] hw/mips/loongson3_virt: Implement IPI support Philippe Mathieu-Daudé
2024-05-16 10:53 ` Jiaxun Yang
2024-06-03 15:35 ` Philippe Mathieu-Daudé
2024-06-04 12:55 ` gaosong
2024-06-04 14:24 ` Philippe Mathieu-Daudé
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