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[83.50.185.174]) by smtp.gmail.com with ESMTPSA id o9sm2430667wrs.4.2021.12.15.09.11.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 15 Dec 2021 09:11:02 -0800 (PST) Message-ID: Date: Wed, 15 Dec 2021 18:11:01 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.3.0 Subject: Re: [RFC PATCH v2 3/5] exec/memattrs: Introduce MemTxAttrs::bus_perm field To: Stefan Hajnoczi , David Hildenbrand , Peter Maydell , "Edgar E . Iglesias" References: <20210823164157.751807-1-philmd@redhat.com> <20210823164157.751807-4-philmd@redhat.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=philmd@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Language: en-US Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=philmd@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -51 X-Spam_score: -5.2 X-Spam_bar: ----- X-Spam_report: (-5.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.719, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.64, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jason Wang , Li Qiang , qemu-devel@nongnu.org, Peter Xu , Qiuhao Li , Alexander Bulekov , qemu-arm@nongnu.org, Gerd Hoffmann , Paolo Bonzini Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 8/24/21 15:08, Stefan Hajnoczi wrote: > On Mon, Aug 23, 2021 at 06:41:55PM +0200, Philippe Mathieu-Daudé wrote: >> Add the 'direct_access' bit to the memory attributes to restrict >> bus master access to ROM/RAM. >> Have read/write accessors return MEMTX_BUS_ERROR if an access is >> restricted and the region is not ROM/RAM ('direct'). >> Add corresponding trace events. >> >> Signed-off-by: Philippe Mathieu-Daudé >> --- >> include/exec/memattrs.h | 21 +++++++++++++++++++++ >> 1 file changed, 21 insertions(+) >> >> diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h >> index 95f2d20d55b..7a94ee75a88 100644 >> --- a/include/exec/memattrs.h >> +++ b/include/exec/memattrs.h >> @@ -14,6 +14,13 @@ >> #ifndef MEMATTRS_H >> #define MEMATTRS_H >> >> +/* Permission to restrict bus memory accesses. See MemTxAttrs::bus_perm */ >> +enum { >> + MEMTXPERM_UNSPECIFIED = 0, >> + MEMTXPERM_UNRESTRICTED = 1, >> + MEMTXPERM_RAM_DEVICE = 2, >> +}; >> + >> /* Every memory transaction has associated with it a set of >> * attributes. Some of these are generic (such as the ID of >> * the bus master); some are specific to a particular kind of >> @@ -35,6 +42,19 @@ typedef struct MemTxAttrs { >> unsigned int secure:1; >> /* Memory access is usermode (unprivileged) */ >> unsigned int user:1; >> + /* >> + * Bus memory access permission. >> + * >> + * Some devices (such DMA) might be restricted to only access >> + * some type of device, such RAM devices. By default memory >> + * accesses are unspecified (MEMTXPERM_UNSPECIFIED), but could be >> + * unrestricted (MEMTXPERM_UNRESTRICTED, similar to an allow list) >> + * or restricted to a type of devices (similar to a deny list). >> + * Currently only RAM devices can be restricted (MEMTXPERM_RAM_DEVICE). > > I don't understand these 3 categories. > > MEMTXPERM_UNSPECIFIED means any MemoryRegion can be accessed? MEMTXPERM_UNSPECIFIED means no change in the current behavior. IOW we haven't reviewed the device, and don't know whether it has to be restricted or not. > What does MEMTXPERM_UNRESTRICTED mean? How does this differ from > MEMTXPERM_UNSPECIFIED? We set MEMTXPERM_UNRESTRICTED when we reviewed a device and are sure it can be accessed any region (even being re-entrant on itself). I understand it like connected via a dual-port on the bus, and allowing read *and* write accesses at the same time... So the device is allowed to access itself, i.e. it can re-program itself in loop and so on. IIUC this is a requested feature for this API. > What exactly does MEMTXPERM_RAM_DEVICE mean? Maybe that only > MemoryRegions where memory_region_is_ram() is true can be accessed? No, it means, while we don't know which bus owner will access the device, the device itself can only access RAMd regions on the bus. I added MEMTXPERM_RAM_DEVICE as the first example, thinking it is the more generic use case. But maybe it is too generic and unuseful, and we need a real bus permission matrix?