* [PATCH qemu v2 01/10] target/riscv: rvv: Add mask agnostic for vv instructions
2022-05-10 18:26 [PATCH qemu v2 00/10] Add mask agnostic behavior for rvv instructions ~eopxd
@ 2022-03-17 7:26 ` ~eopxd
2022-05-11 2:06 ` Weiwei Li
2022-03-17 7:47 ` [PATCH qemu v2 02/10] target/riscv: rvv: Add mask agnostic for vector load / store instructions ~eopxd
` (8 subsequent siblings)
9 siblings, 1 reply; 22+ messages in thread
From: ~eopxd @ 2022-03-17 7:26 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Frank Chang,
WeiWei Li, eop Chen
From: Yueh-Ting (eop) Chen <eop.chen@sifive.com>
According to v-spec, mask agnostic behavior can be either kept as
undisturbed or set elements' bits to all 1s. To distinguish the
difference of mask policies, QEMU should be able to simulate the mask
agnostic behavior as "set mask elements' bits to all 1s".
There are multiple possibility for agnostic elements according to
v-spec. The main intent of this patch-set tries to add option that
can distinguish between mask policies. Setting agnostic elements to
all 1s allows QEMU to express this.
This is the first commit regarding the optional mask agnostic
behavior. Follow-up commits will add this optional behavior
for all rvv instructions.
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/cpu.h | 2 ++
target/riscv/cpu_helper.c | 2 ++
target/riscv/insn_trans/trans_rvv.c.inc | 3 +++
target/riscv/internals.h | 5 +++--
target/riscv/translate.c | 2 ++
target/riscv/vector_helper.c | 8 ++++++++
6 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 61552408b5..4bce3798fc 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -406,6 +406,7 @@ struct RISCVCPUConfig {
bool ext_zve32f;
bool ext_zve64f;
bool rvv_ta_all_1s;
+ bool rvv_ma_all_1s;
uint32_t mvendorid;
uint64_t marchid;
@@ -559,6 +560,7 @@ FIELD(TB_FLAGS, XL, 20, 2)
FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1)
FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1)
FIELD(TB_FLAGS, VTA, 24, 1)
+FIELD(TB_FLAGS, VMA, 25, 1)
#ifdef TARGET_RISCV32
#define riscv_cpu_mxl(env) ((void)(env), MXL_RV32)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index c0641b63cc..ba66b70bd1 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -67,6 +67,8 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax);
flags = FIELD_DP32(flags, TB_FLAGS, VTA,
FIELD_EX64(env->vtype, VTYPE, VTA));
+ flags = FIELD_DP32(flags, TB_FLAGS, VMA,
+ FIELD_EX64(env->vtype, VTYPE, VMA));
} else {
flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);
}
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 27744060dc..63ddd54669 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1258,6 +1258,7 @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn,
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
cpu_env, s->cfg_ptr->vlen / 8,
@@ -1576,6 +1577,7 @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
vreg_ofs(s, a->rs1),
vreg_ofs(s, a->rs2),
@@ -1658,6 +1660,7 @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a,
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
vreg_ofs(s, a->rs1),
vreg_ofs(s, a->rs2),
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index 193ce57a6d..5620fbffb6 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -26,8 +26,9 @@ FIELD(VDATA, VM, 0, 1)
FIELD(VDATA, LMUL, 1, 3)
FIELD(VDATA, VTA, 4, 1)
FIELD(VDATA, VTA_ALL_1S, 5, 1)
-FIELD(VDATA, NF, 6, 4)
-FIELD(VDATA, WD, 6, 1)
+FIELD(VDATA, VMA, 6, 1)
+FIELD(VDATA, NF, 7, 4)
+FIELD(VDATA, WD, 7, 1)
/* float point classify helpers */
target_ulong fclass_h(uint64_t frs1);
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 384ffcc0fa..c7e841da1c 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -95,6 +95,7 @@ typedef struct DisasContext {
int8_t lmul;
uint8_t sew;
uint8_t vta;
+ uint8_t vma;
bool cfg_vta_all_1s;
target_ulong vstart;
bool vl_eq_vlmax;
@@ -1094,6 +1095,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW);
ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3);
ctx->vta = FIELD_EX32(tb_flags, TB_FLAGS, VTA) && cpu->cfg.rvv_ta_all_1s;
+ ctx->vma = FIELD_EX32(tb_flags, TB_FLAGS, VMA) && cpu->cfg.rvv_ma_all_1s;
ctx->cfg_vta_all_1s = cpu->cfg.rvv_ta_all_1s;
ctx->vstart = env->vstart;
ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 28d62565d1..934b283db2 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -127,6 +127,11 @@ static inline uint32_t vext_vta(uint32_t desc)
return FIELD_EX32(simd_data(desc), VDATA, VTA);
}
+static inline uint32_t vext_vma(uint32_t desc)
+{
+ return FIELD_EX32(simd_data(desc), VDATA, VMA);
+}
+
static inline uint32_t vext_vta_all_1s(uint32_t desc)
{
return FIELD_EX32(simd_data(desc), VDATA, VTA_ALL_1S);
@@ -814,10 +819,13 @@ static void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2,
uint32_t vl = env->vl;
uint32_t total_elems = vext_get_total_elems(env, desc, esz);
uint32_t vta = vext_vta(desc);
+ uint32_t vma = vext_vma(desc);
uint32_t i;
for (i = env->vstart; i < vl; i++) {
if (!vm && !vext_elem_mask(v0, i)) {
+ /* set masked-off elements to 1s */
+ vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz);
continue;
}
fn(vd, vs1, vs2, i);
--
2.34.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH qemu v2 01/10] target/riscv: rvv: Add mask agnostic for vv instructions
2022-03-17 7:26 ` [PATCH qemu v2 01/10] target/riscv: rvv: Add mask agnostic for vv instructions ~eopxd
@ 2022-05-11 2:06 ` Weiwei Li
0 siblings, 0 replies; 22+ messages in thread
From: Weiwei Li @ 2022-05-11 2:06 UTC (permalink / raw)
To: ~eopxd, qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Frank Chang,
WeiWei Li, eop Chen
在 2022/3/17 下午3:26, ~eopxd 写道:
> From: Yueh-Ting (eop) Chen <eop.chen@sifive.com>
>
> According to v-spec, mask agnostic behavior can be either kept as
> undisturbed or set elements' bits to all 1s. To distinguish the
> difference of mask policies, QEMU should be able to simulate the mask
> agnostic behavior as "set mask elements' bits to all 1s".
>
> There are multiple possibility for agnostic elements according to
> v-spec. The main intent of this patch-set tries to add option that
> can distinguish between mask policies. Setting agnostic elements to
> all 1s allows QEMU to express this.
>
> This is the first commit regarding the optional mask agnostic
> behavior. Follow-up commits will add this optional behavior
> for all rvv instructions.
>
> Signed-off-by: eop Chen <eop.chen@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/cpu.h | 2 ++
> target/riscv/cpu_helper.c | 2 ++
> target/riscv/insn_trans/trans_rvv.c.inc | 3 +++
> target/riscv/internals.h | 5 +++--
> target/riscv/translate.c | 2 ++
> target/riscv/vector_helper.c | 8 ++++++++
> 6 files changed, 20 insertions(+), 2 deletions(-)
Reviewed-by: Weiwei Li<liweiwei@iscas.ac.cn>
Regards,
Weiwei Li
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 61552408b5..4bce3798fc 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -406,6 +406,7 @@ struct RISCVCPUConfig {
> bool ext_zve32f;
> bool ext_zve64f;
> bool rvv_ta_all_1s;
> + bool rvv_ma_all_1s;
>
> uint32_t mvendorid;
> uint64_t marchid;
> @@ -559,6 +560,7 @@ FIELD(TB_FLAGS, XL, 20, 2)
> FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1)
> FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1)
> FIELD(TB_FLAGS, VTA, 24, 1)
> +FIELD(TB_FLAGS, VMA, 25, 1)
>
> #ifdef TARGET_RISCV32
> #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32)
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index c0641b63cc..ba66b70bd1 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -67,6 +67,8 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
> flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax);
> flags = FIELD_DP32(flags, TB_FLAGS, VTA,
> FIELD_EX64(env->vtype, VTYPE, VTA));
> + flags = FIELD_DP32(flags, TB_FLAGS, VMA,
> + FIELD_EX64(env->vtype, VTYPE, VMA));
> } else {
> flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);
> }
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 27744060dc..63ddd54669 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -1258,6 +1258,7 @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn,
> data = FIELD_DP32(data, VDATA, VM, a->vm);
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> data = FIELD_DP32(data, VDATA, VTA, s->vta);
> + data = FIELD_DP32(data, VDATA, VMA, s->vma);
> tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
> vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
> cpu_env, s->cfg_ptr->vlen / 8,
> @@ -1576,6 +1577,7 @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
> data = FIELD_DP32(data, VDATA, VM, a->vm);
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> data = FIELD_DP32(data, VDATA, VTA, s->vta);
> + data = FIELD_DP32(data, VDATA, VMA, s->vma);
> tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
> vreg_ofs(s, a->rs1),
> vreg_ofs(s, a->rs2),
> @@ -1658,6 +1660,7 @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a,
> data = FIELD_DP32(data, VDATA, VM, a->vm);
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> data = FIELD_DP32(data, VDATA, VTA, s->vta);
> + data = FIELD_DP32(data, VDATA, VMA, s->vma);
> tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
> vreg_ofs(s, a->rs1),
> vreg_ofs(s, a->rs2),
> diff --git a/target/riscv/internals.h b/target/riscv/internals.h
> index 193ce57a6d..5620fbffb6 100644
> --- a/target/riscv/internals.h
> +++ b/target/riscv/internals.h
> @@ -26,8 +26,9 @@ FIELD(VDATA, VM, 0, 1)
> FIELD(VDATA, LMUL, 1, 3)
> FIELD(VDATA, VTA, 4, 1)
> FIELD(VDATA, VTA_ALL_1S, 5, 1)
> -FIELD(VDATA, NF, 6, 4)
> -FIELD(VDATA, WD, 6, 1)
> +FIELD(VDATA, VMA, 6, 1)
> +FIELD(VDATA, NF, 7, 4)
> +FIELD(VDATA, WD, 7, 1)
>
> /* float point classify helpers */
> target_ulong fclass_h(uint64_t frs1);
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 384ffcc0fa..c7e841da1c 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -95,6 +95,7 @@ typedef struct DisasContext {
> int8_t lmul;
> uint8_t sew;
> uint8_t vta;
> + uint8_t vma;
> bool cfg_vta_all_1s;
> target_ulong vstart;
> bool vl_eq_vlmax;
> @@ -1094,6 +1095,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
> ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW);
> ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3);
> ctx->vta = FIELD_EX32(tb_flags, TB_FLAGS, VTA) && cpu->cfg.rvv_ta_all_1s;
> + ctx->vma = FIELD_EX32(tb_flags, TB_FLAGS, VMA) && cpu->cfg.rvv_ma_all_1s;
> ctx->cfg_vta_all_1s = cpu->cfg.rvv_ta_all_1s;
> ctx->vstart = env->vstart;
> ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 28d62565d1..934b283db2 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -127,6 +127,11 @@ static inline uint32_t vext_vta(uint32_t desc)
> return FIELD_EX32(simd_data(desc), VDATA, VTA);
> }
>
> +static inline uint32_t vext_vma(uint32_t desc)
> +{
> + return FIELD_EX32(simd_data(desc), VDATA, VMA);
> +}
> +
> static inline uint32_t vext_vta_all_1s(uint32_t desc)
> {
> return FIELD_EX32(simd_data(desc), VDATA, VTA_ALL_1S);
> @@ -814,10 +819,13 @@ static void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2,
> uint32_t vl = env->vl;
> uint32_t total_elems = vext_get_total_elems(env, desc, esz);
> uint32_t vta = vext_vta(desc);
> + uint32_t vma = vext_vma(desc);
> uint32_t i;
>
> for (i = env->vstart; i < vl; i++) {
> if (!vm && !vext_elem_mask(v0, i)) {
> + /* set masked-off elements to 1s */
> + vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz);
> continue;
> }
> fn(vd, vs1, vs2, i);
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH qemu v2 02/10] target/riscv: rvv: Add mask agnostic for vector load / store instructions
2022-05-10 18:26 [PATCH qemu v2 00/10] Add mask agnostic behavior for rvv instructions ~eopxd
2022-03-17 7:26 ` [PATCH qemu v2 01/10] target/riscv: rvv: Add mask agnostic for vv instructions ~eopxd
@ 2022-03-17 7:47 ` ~eopxd
2022-05-11 1:59 ` Weiwei Li
2022-05-11 2:53 ` Weiwei Li
2022-03-17 8:38 ` [PATCH qemu v2 03/10] target/riscv: rvv: Add mask agnostic for vx instructions ~eopxd
` (7 subsequent siblings)
9 siblings, 2 replies; 22+ messages in thread
From: ~eopxd @ 2022-03-17 7:47 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Frank Chang,
WeiWei Li, eop Chen
From: Yueh-Ting (eop) Chen <eop.chen@sifive.com>
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 9 +++++++
target/riscv/vector_helper.c | 35 +++++++++++++++++--------
2 files changed, 33 insertions(+), 11 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 63ddd54669..9a2d54313a 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -712,6 +712,7 @@ static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t eew)
data = FIELD_DP32(data, VDATA, LMUL, emul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
return ldst_us_trans(a->rd, a->rs1, data, fn, s, false);
}
@@ -750,6 +751,7 @@ static bool st_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t eew)
data = FIELD_DP32(data, VDATA, LMUL, emul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
return ldst_us_trans(a->rd, a->rs1, data, fn, s, true);
}
@@ -778,6 +780,7 @@ static bool ld_us_mask_op(DisasContext *s, arg_vlm_v *a, uint8_t eew)
data = FIELD_DP32(data, VDATA, NF, 1);
/* Mask destination register are always tail-agnostic */
data = FIELD_DP32(data, VDATA, VTA, s->cfg_vta_all_1s);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
return ldst_us_trans(a->rd, a->rs1, data, fn, s, false);
}
@@ -797,6 +800,7 @@ static bool st_us_mask_op(DisasContext *s, arg_vsm_v *a, uint8_t eew)
data = FIELD_DP32(data, VDATA, NF, 1);
/* Mask destination register are always tail-agnostic */
data = FIELD_DP32(data, VDATA, VTA, s->cfg_vta_all_1s);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
return ldst_us_trans(a->rd, a->rs1, data, fn, s, true);
}
@@ -869,6 +873,7 @@ static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
data = FIELD_DP32(data, VDATA, LMUL, emul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, false);
}
@@ -899,6 +904,7 @@ static bool st_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
data = FIELD_DP32(data, VDATA, LMUL, emul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
fn = fns[eew];
if (fn == NULL) {
return false;
@@ -1000,6 +1006,7 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
data = FIELD_DP32(data, VDATA, LMUL, emul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, false);
}
@@ -1053,6 +1060,7 @@ static bool st_index_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
data = FIELD_DP32(data, VDATA, LMUL, emul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, true);
}
@@ -1119,6 +1127,7 @@ static bool ldff_op(DisasContext *s, arg_r2nfvm *a, uint8_t eew)
data = FIELD_DP32(data, VDATA, LMUL, emul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
return ldff_trans(a->rd, a->rs1, data, fn, s);
}
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 934b283db2..89eea33eb3 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -282,14 +282,18 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
uint32_t esz = 1 << log2_esz;
uint32_t total_elems = vext_get_total_elems(env, desc, esz);
uint32_t vta = vext_vta(desc);
+ uint32_t vma = vext_vma(desc);
for (i = env->vstart; i < env->vl; i++, env->vstart++) {
- if (!vm && !vext_elem_mask(v0, i)) {
- continue;
- }
-
k = 0;
while (k < nf) {
+ if (!vm && !vext_elem_mask(v0, i)) {
+ /* set masked-off elements to 1s */
+ vext_set_elems_1s(vd, vma,(i + k * max_elems) * esz,
+ (i + k * max_elems + 1) * esz);
+ k++;
+ continue;
+ }
target_ulong addr = base + stride * i + (k << log2_esz);
ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, ra);
k++;
@@ -481,15 +485,19 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
uint32_t esz = 1 << log2_esz;
uint32_t total_elems = vext_get_total_elems(env, desc, esz);
uint32_t vta = vext_vta(desc);
+ uint32_t vma = vext_vma(desc);
/* load bytes from guest memory */
for (i = env->vstart; i < env->vl; i++, env->vstart++) {
- if (!vm && !vext_elem_mask(v0, i)) {
- continue;
- }
-
k = 0;
while (k < nf) {
+ if (!vm && !vext_elem_mask(v0, i)) {
+ /* set masked-off elements to 1s */
+ vext_set_elems_1s(vd, vma,(i + k * max_elems) * esz,
+ (i + k * max_elems + 1) * esz);
+ k++;
+ continue;
+ }
abi_ptr addr = get_index_addr(base, i, vs2) + (k << log2_esz);
ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, ra);
k++;
@@ -578,6 +586,7 @@ vext_ldff(void *vd, void *v0, target_ulong base,
uint32_t esz = 1 << log2_esz;
uint32_t total_elems = vext_get_total_elems(env, desc, esz);
uint32_t vta = vext_vta(desc);
+ uint32_t vma = vext_vma(desc);
target_ulong addr, offset, remain;
/* probe every access*/
@@ -623,10 +632,14 @@ ProbeSuccess:
}
for (i = env->vstart; i < env->vl; i++) {
k = 0;
- if (!vm && !vext_elem_mask(v0, i)) {
- continue;
- }
while (k < nf) {
+ if (!vm && !vext_elem_mask(v0, i)) {
+ /* set masked-off elements to 1s */
+ vext_set_elems_1s(vd, vma,(i + k * max_elems) * esz,
+ (i + k * max_elems + 1) * esz);
+ k++;
+ continue;
+ }
target_ulong addr = base + ((i * nf + k) << log2_esz);
ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, ra);
k++;
--
2.34.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH qemu v2 02/10] target/riscv: rvv: Add mask agnostic for vector load / store instructions
2022-03-17 7:47 ` [PATCH qemu v2 02/10] target/riscv: rvv: Add mask agnostic for vector load / store instructions ~eopxd
@ 2022-05-11 1:59 ` Weiwei Li
2022-05-11 2:53 ` Weiwei Li
1 sibling, 0 replies; 22+ messages in thread
From: Weiwei Li @ 2022-05-11 1:59 UTC (permalink / raw)
To: ~eopxd, qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Frank Chang,
WeiWei Li, eop Chen
在 2022/3/17 下午3:47, ~eopxd 写道:
> From: Yueh-Ting (eop) Chen <eop.chen@sifive.com>
>
> Signed-off-by: eop Chen <eop.chen@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 9 +++++++
> target/riscv/vector_helper.c | 35 +++++++++++++++++--------
> 2 files changed, 33 insertions(+), 11 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 63ddd54669..9a2d54313a 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -712,6 +712,7 @@ static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t eew)
> data = FIELD_DP32(data, VDATA, LMUL, emul);
> data = FIELD_DP32(data, VDATA, NF, a->nf);
> data = FIELD_DP32(data, VDATA, VTA, s->vta);
> + data = FIELD_DP32(data, VDATA, VMA, s->vma);
> return ldst_us_trans(a->rd, a->rs1, data, fn, s, false);
> }
>
> @@ -750,6 +751,7 @@ static bool st_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t eew)
> data = FIELD_DP32(data, VDATA, LMUL, emul);
> data = FIELD_DP32(data, VDATA, NF, a->nf);
> data = FIELD_DP32(data, VDATA, VTA, s->vta);
> + data = FIELD_DP32(data, VDATA, VMA, s->vma);
> return ldst_us_trans(a->rd, a->rs1, data, fn, s, true);
> }
>
> @@ -778,6 +780,7 @@ static bool ld_us_mask_op(DisasContext *s, arg_vlm_v *a, uint8_t eew)
> data = FIELD_DP32(data, VDATA, NF, 1);
> /* Mask destination register are always tail-agnostic */
> data = FIELD_DP32(data, VDATA, VTA, s->cfg_vta_all_1s);
> + data = FIELD_DP32(data, VDATA, VMA, s->vma);
> return ldst_us_trans(a->rd, a->rs1, data, fn, s, false);
> }
>
> @@ -797,6 +800,7 @@ static bool st_us_mask_op(DisasContext *s, arg_vsm_v *a, uint8_t eew)
> data = FIELD_DP32(data, VDATA, NF, 1);
> /* Mask destination register are always tail-agnostic */
> data = FIELD_DP32(data, VDATA, VTA, s->cfg_vta_all_1s);
> + data = FIELD_DP32(data, VDATA, VMA, s->vma);
> return ldst_us_trans(a->rd, a->rs1, data, fn, s, true);
> }
>
> @@ -869,6 +873,7 @@ static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
> data = FIELD_DP32(data, VDATA, LMUL, emul);
> data = FIELD_DP32(data, VDATA, NF, a->nf);
> data = FIELD_DP32(data, VDATA, VTA, s->vta);
> + data = FIELD_DP32(data, VDATA, VMA, s->vma);
> return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, false);
> }
>
> @@ -899,6 +904,7 @@ static bool st_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
> data = FIELD_DP32(data, VDATA, LMUL, emul);
> data = FIELD_DP32(data, VDATA, NF, a->nf);
> data = FIELD_DP32(data, VDATA, VTA, s->vta);
> + data = FIELD_DP32(data, VDATA, VMA, s->vma);
> fn = fns[eew];
> if (fn == NULL) {
> return false;
> @@ -1000,6 +1006,7 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
> data = FIELD_DP32(data, VDATA, LMUL, emul);
> data = FIELD_DP32(data, VDATA, NF, a->nf);
> data = FIELD_DP32(data, VDATA, VTA, s->vta);
> + data = FIELD_DP32(data, VDATA, VMA, s->vma);
> return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, false);
> }
>
> @@ -1053,6 +1060,7 @@ static bool st_index_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
> data = FIELD_DP32(data, VDATA, LMUL, emul);
> data = FIELD_DP32(data, VDATA, NF, a->nf);
> data = FIELD_DP32(data, VDATA, VTA, s->vta);
> + data = FIELD_DP32(data, VDATA, VMA, s->vma);
> return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, true);
> }
>
> @@ -1119,6 +1127,7 @@ static bool ldff_op(DisasContext *s, arg_r2nfvm *a, uint8_t eew)
> data = FIELD_DP32(data, VDATA, LMUL, emul);
> data = FIELD_DP32(data, VDATA, NF, a->nf);
> data = FIELD_DP32(data, VDATA, VTA, s->vta);
> + data = FIELD_DP32(data, VDATA, VMA, s->vma);
> return ldff_trans(a->rd, a->rs1, data, fn, s);
> }
>
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 934b283db2..89eea33eb3 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -282,14 +282,18 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
> uint32_t esz = 1 << log2_esz;
> uint32_t total_elems = vext_get_total_elems(env, desc, esz);
> uint32_t vta = vext_vta(desc);
> + uint32_t vma = vext_vma(desc);
>
> for (i = env->vstart; i < env->vl; i++, env->vstart++) {
> - if (!vm && !vext_elem_mask(v0, i)) {
> - continue;
> - }
> -
> k = 0;
> while (k < nf) {
> + if (!vm && !vext_elem_mask(v0, i)) {
> + /* set masked-off elements to 1s */
> + vext_set_elems_1s(vd, vma,(i + k * max_elems) * esz,
seems lack a space here. the same to following cases.
Regards,
Weiwei Li
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH qemu v2 02/10] target/riscv: rvv: Add mask agnostic for vector load / store instructions
2022-03-17 7:47 ` [PATCH qemu v2 02/10] target/riscv: rvv: Add mask agnostic for vector load / store instructions ~eopxd
2022-05-11 1:59 ` Weiwei Li
@ 2022-05-11 2:53 ` Weiwei Li
1 sibling, 0 replies; 22+ messages in thread
From: Weiwei Li @ 2022-05-11 2:53 UTC (permalink / raw)
To: ~eopxd, qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Frank Chang,
WeiWei Li, eop Chen
在 2022/3/17 下午3:47, ~eopxd 写道:
> From: Yueh-Ting (eop) Chen <eop.chen@sifive.com>
>
> Signed-off-by: eop Chen <eop.chen@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 9 +++++++
> target/riscv/vector_helper.c | 35 +++++++++++++++++--------
> 2 files changed, 33 insertions(+), 11 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 63ddd54669..9a2d54313a 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -712,6 +712,7 @@ static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t eew)
> data = FIELD_DP32(data, VDATA, LMUL, emul);
> data = FIELD_DP32(data, VDATA, NF, a->nf);
> data = FIELD_DP32(data, VDATA, VTA, s->vta);
> + data = FIELD_DP32(data, VDATA, VMA, s->vma);
> return ldst_us_trans(a->rd, a->rs1, data, fn, s, false);
> }
>
> @@ -750,6 +751,7 @@ static bool st_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t eew)
> data = FIELD_DP32(data, VDATA, LMUL, emul);
> data = FIELD_DP32(data, VDATA, NF, a->nf);
> data = FIELD_DP32(data, VDATA, VTA, s->vta);
> + data = FIELD_DP32(data, VDATA, VMA, s->vma);
> return ldst_us_trans(a->rd, a->rs1, data, fn, s, true);
> }
>
> @@ -778,6 +780,7 @@ static bool ld_us_mask_op(DisasContext *s, arg_vlm_v *a, uint8_t eew)
> data = FIELD_DP32(data, VDATA, NF, 1);
> /* Mask destination register are always tail-agnostic */
> data = FIELD_DP32(data, VDATA, VTA, s->cfg_vta_all_1s);
> + data = FIELD_DP32(data, VDATA, VMA, s->vma);
> return ldst_us_trans(a->rd, a->rs1, data, fn, s, false);
> }
>
> @@ -797,6 +800,7 @@ static bool st_us_mask_op(DisasContext *s, arg_vsm_v *a, uint8_t eew)
> data = FIELD_DP32(data, VDATA, NF, 1);
> /* Mask destination register are always tail-agnostic */
> data = FIELD_DP32(data, VDATA, VTA, s->cfg_vta_all_1s);
> + data = FIELD_DP32(data, VDATA, VMA, s->vma);
> return ldst_us_trans(a->rd, a->rs1, data, fn, s, true);
> }
>
> @@ -869,6 +873,7 @@ static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
> data = FIELD_DP32(data, VDATA, LMUL, emul);
> data = FIELD_DP32(data, VDATA, NF, a->nf);
> data = FIELD_DP32(data, VDATA, VTA, s->vta);
> + data = FIELD_DP32(data, VDATA, VMA, s->vma);
> return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, false);
> }
>
> @@ -899,6 +904,7 @@ static bool st_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
> data = FIELD_DP32(data, VDATA, LMUL, emul);
> data = FIELD_DP32(data, VDATA, NF, a->nf);
> data = FIELD_DP32(data, VDATA, VTA, s->vta);
> + data = FIELD_DP32(data, VDATA, VMA, s->vma);
> fn = fns[eew];
> if (fn == NULL) {
> return false;
> @@ -1000,6 +1006,7 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
> data = FIELD_DP32(data, VDATA, LMUL, emul);
> data = FIELD_DP32(data, VDATA, NF, a->nf);
> data = FIELD_DP32(data, VDATA, VTA, s->vta);
> + data = FIELD_DP32(data, VDATA, VMA, s->vma);
> return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, false);
> }
>
> @@ -1053,6 +1060,7 @@ static bool st_index_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
> data = FIELD_DP32(data, VDATA, LMUL, emul);
> data = FIELD_DP32(data, VDATA, NF, a->nf);
> data = FIELD_DP32(data, VDATA, VTA, s->vta);
> + data = FIELD_DP32(data, VDATA, VMA, s->vma);
> return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, true);
> }
>
> @@ -1119,6 +1127,7 @@ static bool ldff_op(DisasContext *s, arg_r2nfvm *a, uint8_t eew)
> data = FIELD_DP32(data, VDATA, LMUL, emul);
> data = FIELD_DP32(data, VDATA, NF, a->nf);
> data = FIELD_DP32(data, VDATA, VTA, s->vta);
> + data = FIELD_DP32(data, VDATA, VMA, s->vma);
> return ldff_trans(a->rd, a->rs1, data, fn, s);
> }
>
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 934b283db2..89eea33eb3 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -282,14 +282,18 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
> uint32_t esz = 1 << log2_esz;
> uint32_t total_elems = vext_get_total_elems(env, desc, esz);
> uint32_t vta = vext_vta(desc);
> + uint32_t vma = vext_vma(desc);
>
> for (i = env->vstart; i < env->vl; i++, env->vstart++) {
> - if (!vm && !vext_elem_mask(v0, i)) {
> - continue;
> - }
> -
> k = 0;
> while (k < nf) {
> + if (!vm && !vext_elem_mask(v0, i)) {
> + /* set masked-off elements to 1s */
> + vext_set_elems_1s(vd, vma,(i + k * max_elems) * esz,
> + (i + k * max_elems + 1) * esz);
> + k++;
> + continue;
There is another question here:
this function is reused by load&store. However vd is used as source for
store.
So we cannot set it without distinguish load and store here. The same to
following load&store functions.
Maybe we can set vma to zero for stores(it seems have no effect on the
function for stores).
Regards,
Weiwei Li
> + }
> target_ulong addr = base + stride * i + (k << log2_esz);
> ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, ra);
> k++;
> @@ -481,15 +485,19 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
> uint32_t esz = 1 << log2_esz;
> uint32_t total_elems = vext_get_total_elems(env, desc, esz);
> uint32_t vta = vext_vta(desc);
> + uint32_t vma = vext_vma(desc);
>
> /* load bytes from guest memory */
> for (i = env->vstart; i < env->vl; i++, env->vstart++) {
> - if (!vm && !vext_elem_mask(v0, i)) {
> - continue;
> - }
> -
> k = 0;
> while (k < nf) {
> + if (!vm && !vext_elem_mask(v0, i)) {
> + /* set masked-off elements to 1s */
> + vext_set_elems_1s(vd, vma,(i + k * max_elems) * esz,
> + (i + k * max_elems + 1) * esz);
> + k++;
> + continue;
> + }
> abi_ptr addr = get_index_addr(base, i, vs2) + (k << log2_esz);
> ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, ra);
> k++;
> @@ -578,6 +586,7 @@ vext_ldff(void *vd, void *v0, target_ulong base,
> uint32_t esz = 1 << log2_esz;
> uint32_t total_elems = vext_get_total_elems(env, desc, esz);
> uint32_t vta = vext_vta(desc);
> + uint32_t vma = vext_vma(desc);
> target_ulong addr, offset, remain;
>
> /* probe every access*/
> @@ -623,10 +632,14 @@ ProbeSuccess:
> }
> for (i = env->vstart; i < env->vl; i++) {
> k = 0;
> - if (!vm && !vext_elem_mask(v0, i)) {
> - continue;
> - }
> while (k < nf) {
> + if (!vm && !vext_elem_mask(v0, i)) {
> + /* set masked-off elements to 1s */
> + vext_set_elems_1s(vd, vma,(i + k * max_elems) * esz,
> + (i + k * max_elems + 1) * esz);
> + k++;
> + continue;
> + }
> target_ulong addr = base + ((i * nf + k) << log2_esz);
> ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, ra);
> k++;
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH qemu v2 03/10] target/riscv: rvv: Add mask agnostic for vx instructions
2022-05-10 18:26 [PATCH qemu v2 00/10] Add mask agnostic behavior for rvv instructions ~eopxd
2022-03-17 7:26 ` [PATCH qemu v2 01/10] target/riscv: rvv: Add mask agnostic for vv instructions ~eopxd
2022-03-17 7:47 ` [PATCH qemu v2 02/10] target/riscv: rvv: Add mask agnostic for vector load / store instructions ~eopxd
@ 2022-03-17 8:38 ` ~eopxd
2022-05-11 2:07 ` Weiwei Li
2022-03-17 8:43 ` [PATCH qemu v2 04/10] target/riscv: rvv: Add mask agnostic for vector integer shift instructions ~eopxd
` (6 subsequent siblings)
9 siblings, 1 reply; 22+ messages in thread
From: ~eopxd @ 2022-03-17 8:38 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Frank Chang,
WeiWei Li, eop Chen
From: Yueh-Ting (eop) Chen <eop.chen@sifive.com>
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 2 ++
target/riscv/vector_helper.c | 3 +++
2 files changed, 5 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 9a2d54313a..de8dda31fe 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1316,6 +1316,7 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, VTA, s->vta);
data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
s->cfg_ptr->vlen / 8, data));
@@ -1493,6 +1494,7 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, VTA, s->vta);
data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
s->cfg_ptr->vlen / 8, data));
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 89eea33eb3..98c9f21182 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -901,10 +901,13 @@ static void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2,
uint32_t vl = env->vl;
uint32_t total_elems = vext_get_total_elems(env, desc, esz);
uint32_t vta = vext_vta(desc);
+ uint32_t vma = vext_vma(desc);
uint32_t i;
for (i = env->vstart; i < vl; i++) {
if (!vm && !vext_elem_mask(v0, i)) {
+ /* set masked-off elements to 1s */
+ vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz);
continue;
}
fn(vd, s1, vs2, i);
--
2.34.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH qemu v2 03/10] target/riscv: rvv: Add mask agnostic for vx instructions
2022-03-17 8:38 ` [PATCH qemu v2 03/10] target/riscv: rvv: Add mask agnostic for vx instructions ~eopxd
@ 2022-05-11 2:07 ` Weiwei Li
0 siblings, 0 replies; 22+ messages in thread
From: Weiwei Li @ 2022-05-11 2:07 UTC (permalink / raw)
To: ~eopxd, qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Frank Chang,
WeiWei Li, eop Chen
在 2022/3/17 下午4:38, ~eopxd 写道:
> From: Yueh-Ting (eop) Chen <eop.chen@sifive.com>
>
> Signed-off-by: eop Chen <eop.chen@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 2 ++
> target/riscv/vector_helper.c | 3 +++
> 2 files changed, 5 insertions(+)
Reviewed-by: Weiwei Li<liweiwei@iscas.ac.cn>
Regards,
Weiwei Li
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 9a2d54313a..de8dda31fe 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -1316,6 +1316,7 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> data = FIELD_DP32(data, VDATA, VTA, s->vta);
> data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);
> + data = FIELD_DP32(data, VDATA, VMA, s->vma);
> desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
> s->cfg_ptr->vlen / 8, data));
>
> @@ -1493,6 +1494,7 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> data = FIELD_DP32(data, VDATA, VTA, s->vta);
> data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);
> + data = FIELD_DP32(data, VDATA, VMA, s->vma);
> desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
> s->cfg_ptr->vlen / 8, data));
>
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 89eea33eb3..98c9f21182 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -901,10 +901,13 @@ static void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2,
> uint32_t vl = env->vl;
> uint32_t total_elems = vext_get_total_elems(env, desc, esz);
> uint32_t vta = vext_vta(desc);
> + uint32_t vma = vext_vma(desc);
> uint32_t i;
>
> for (i = env->vstart; i < vl; i++) {
> if (!vm && !vext_elem_mask(v0, i)) {
> + /* set masked-off elements to 1s */
> + vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz);
> continue;
> }
> fn(vd, s1, vs2, i);
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH qemu v2 04/10] target/riscv: rvv: Add mask agnostic for vector integer shift instructions
2022-05-10 18:26 [PATCH qemu v2 00/10] Add mask agnostic behavior for rvv instructions ~eopxd
` (2 preceding siblings ...)
2022-03-17 8:38 ` [PATCH qemu v2 03/10] target/riscv: rvv: Add mask agnostic for vx instructions ~eopxd
@ 2022-03-17 8:43 ` ~eopxd
2022-05-11 2:09 ` Weiwei Li
2022-03-17 8:46 ` [PATCH qemu v2 05/10] target/riscv: rvv: Add mask agnostic for vector integer comparison instructions ~eopxd
` (5 subsequent siblings)
9 siblings, 1 reply; 22+ messages in thread
From: ~eopxd @ 2022-03-17 8:43 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Frank Chang,
WeiWei Li, eop Chen
From: Yueh-Ting (eop) Chen <eop.chen@sifive.com>
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 1 +
target/riscv/vector_helper.c | 7 +++++++
2 files changed, 8 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index de8dda31fe..ffbbbf9b3a 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1946,6 +1946,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, \
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 98c9f21182..0583602528 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -1300,10 +1300,13 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
uint32_t esz = sizeof(TS1); \
uint32_t total_elems = vext_get_total_elems(env, desc, esz); \
uint32_t vta = vext_vta(desc); \
+ uint32_t vma = vext_vma(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
if (!vm && !vext_elem_mask(v0, i)) { \
+ /* set masked-off elements to 1s */ \
+ vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); \
continue; \
} \
TS1 s1 = *((TS1 *)vs1 + HS1(i)); \
@@ -1341,10 +1344,14 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
uint32_t total_elems = \
vext_get_total_elems(env, desc, esz); \
uint32_t vta = vext_vta(desc); \
+ uint32_t vma = vext_vma(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
if (!vm && !vext_elem_mask(v0, i)) { \
+ /* set masked-off elements to 1s */ \
+ vext_set_elems_1s(vd, vma, i * esz, \
+ (i + 1) * esz); \
continue; \
} \
TS2 s2 = *((TS2 *)vs2 + HS2(i)); \
--
2.34.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH qemu v2 04/10] target/riscv: rvv: Add mask agnostic for vector integer shift instructions
2022-03-17 8:43 ` [PATCH qemu v2 04/10] target/riscv: rvv: Add mask agnostic for vector integer shift instructions ~eopxd
@ 2022-05-11 2:09 ` Weiwei Li
0 siblings, 0 replies; 22+ messages in thread
From: Weiwei Li @ 2022-05-11 2:09 UTC (permalink / raw)
To: ~eopxd, qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Frank Chang,
WeiWei Li, eop Chen
在 2022/3/17 下午4:43, ~eopxd 写道:
> From: Yueh-Ting (eop) Chen <eop.chen@sifive.com>
>
> Signed-off-by: eop Chen <eop.chen@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 1 +
> target/riscv/vector_helper.c | 7 +++++++
> 2 files changed, 8 insertions(+)
Reviewed-by: Weiwei Li<liweiwei@iscas.ac.cn>
Regards,
Weiwei Li
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index de8dda31fe..ffbbbf9b3a 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -1946,6 +1946,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
> data = FIELD_DP32(data, VDATA, VM, a->vm); \
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
> data = FIELD_DP32(data, VDATA, VTA, s->vta); \
> + data = FIELD_DP32(data, VDATA, VMA, s->vma); \
> tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
> vreg_ofs(s, a->rs1), \
> vreg_ofs(s, a->rs2), cpu_env, \
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 98c9f21182..0583602528 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -1300,10 +1300,13 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
> uint32_t esz = sizeof(TS1); \
> uint32_t total_elems = vext_get_total_elems(env, desc, esz); \
> uint32_t vta = vext_vta(desc); \
> + uint32_t vma = vext_vma(desc); \
> uint32_t i; \
> \
> for (i = env->vstart; i < vl; i++) { \
> if (!vm && !vext_elem_mask(v0, i)) { \
> + /* set masked-off elements to 1s */ \
> + vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); \
> continue; \
> } \
> TS1 s1 = *((TS1 *)vs1 + HS1(i)); \
> @@ -1341,10 +1344,14 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
> uint32_t total_elems = \
> vext_get_total_elems(env, desc, esz); \
> uint32_t vta = vext_vta(desc); \
> + uint32_t vma = vext_vma(desc); \
> uint32_t i; \
> \
> for (i = env->vstart; i < vl; i++) { \
> if (!vm && !vext_elem_mask(v0, i)) { \
> + /* set masked-off elements to 1s */ \
> + vext_set_elems_1s(vd, vma, i * esz, \
> + (i + 1) * esz); \
> continue; \
> } \
> TS2 s2 = *((TS2 *)vs2 + HS2(i)); \
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH qemu v2 05/10] target/riscv: rvv: Add mask agnostic for vector integer comparison instructions
2022-05-10 18:26 [PATCH qemu v2 00/10] Add mask agnostic behavior for rvv instructions ~eopxd
` (3 preceding siblings ...)
2022-03-17 8:43 ` [PATCH qemu v2 04/10] target/riscv: rvv: Add mask agnostic for vector integer shift instructions ~eopxd
@ 2022-03-17 8:46 ` ~eopxd
2022-05-11 2:24 ` Weiwei Li
2022-03-17 8:52 ` [PATCH qemu v2 06/10] target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic instructions ~eopxd
` (4 subsequent siblings)
9 siblings, 1 reply; 22+ messages in thread
From: ~eopxd @ 2022-03-17 8:46 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Frank Chang,
WeiWei Li, eop Chen
From: Yueh-Ting (eop) Chen <eop.chen@sifive.com>
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 1 +
target/riscv/vector_helper.c | 10 ++++++++++
2 files changed, 11 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index ffbbbf9b3a..5cbf323c18 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1753,6 +1753,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
data = FIELD_DP32(data, VDATA, VTA, s->vta); \
data = \
FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);\
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, \
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 0583602528..9bb259586d 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -1406,12 +1406,17 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
uint32_t vl = env->vl; \
uint32_t total_elems = env_archcpu(env)->cfg.vlen; \
uint32_t vta_all_1s = vext_vta_all_1s(desc); \
+ uint32_t vma = vext_vma(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
if (!vm && !vext_elem_mask(v0, i)) { \
+ /* set masked-off elements to 1s */ \
+ if (vma) { \
+ vext_set_elem_mask(vd, i, 1); \
+ } \
continue; \
} \
vext_set_elem_mask(vd, i, DO_OP(s2, s1)); \
@@ -1464,11 +1469,16 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
uint32_t vl = env->vl; \
uint32_t total_elems = env_archcpu(env)->cfg.vlen; \
uint32_t vta_all_1s = vext_vta_all_1s(desc); \
+ uint32_t vma = vext_vma(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
if (!vm && !vext_elem_mask(v0, i)) { \
+ /* set masked-off elements to 1s */ \
+ if (vma) { \
+ vext_set_elem_mask(vd, i, 1); \
+ } \
continue; \
} \
vext_set_elem_mask(vd, i, \
--
2.34.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH qemu v2 05/10] target/riscv: rvv: Add mask agnostic for vector integer comparison instructions
2022-03-17 8:46 ` [PATCH qemu v2 05/10] target/riscv: rvv: Add mask agnostic for vector integer comparison instructions ~eopxd
@ 2022-05-11 2:24 ` Weiwei Li
0 siblings, 0 replies; 22+ messages in thread
From: Weiwei Li @ 2022-05-11 2:24 UTC (permalink / raw)
To: ~eopxd, qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Frank Chang,
WeiWei Li, eop Chen
在 2022/3/17 下午4:46, ~eopxd 写道:
> From: Yueh-Ting (eop) Chen <eop.chen@sifive.com>
>
> Signed-off-by: eop Chen <eop.chen@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 1 +
> target/riscv/vector_helper.c | 10 ++++++++++
> 2 files changed, 11 insertions(+)
Reviewed-by: Weiwei Li<liweiwei@iscas.ac.cn>
Regards,
Weiwei Li
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index ffbbbf9b3a..5cbf323c18 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -1753,6 +1753,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
> data = FIELD_DP32(data, VDATA, VTA, s->vta); \
> data = \
> FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);\
> + data = FIELD_DP32(data, VDATA, VMA, s->vma); \
> tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
> vreg_ofs(s, a->rs1), \
> vreg_ofs(s, a->rs2), cpu_env, \
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 0583602528..9bb259586d 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -1406,12 +1406,17 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
> uint32_t vl = env->vl; \
> uint32_t total_elems = env_archcpu(env)->cfg.vlen; \
> uint32_t vta_all_1s = vext_vta_all_1s(desc); \
> + uint32_t vma = vext_vma(desc); \
> uint32_t i; \
> \
> for (i = env->vstart; i < vl; i++) { \
> ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
> ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
> if (!vm && !vext_elem_mask(v0, i)) { \
> + /* set masked-off elements to 1s */ \
> + if (vma) { \
> + vext_set_elem_mask(vd, i, 1); \
> + } \
> continue; \
> } \
> vext_set_elem_mask(vd, i, DO_OP(s2, s1)); \
> @@ -1464,11 +1469,16 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
> uint32_t vl = env->vl; \
> uint32_t total_elems = env_archcpu(env)->cfg.vlen; \
> uint32_t vta_all_1s = vext_vta_all_1s(desc); \
> + uint32_t vma = vext_vma(desc); \
> uint32_t i; \
> \
> for (i = env->vstart; i < vl; i++) { \
> ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
> if (!vm && !vext_elem_mask(v0, i)) { \
> + /* set masked-off elements to 1s */ \
> + if (vma) { \
> + vext_set_elem_mask(vd, i, 1); \
> + } \
> continue; \
> } \
> vext_set_elem_mask(vd, i, \
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH qemu v2 06/10] target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic instructions
2022-05-10 18:26 [PATCH qemu v2 00/10] Add mask agnostic behavior for rvv instructions ~eopxd
` (4 preceding siblings ...)
2022-03-17 8:46 ` [PATCH qemu v2 05/10] target/riscv: rvv: Add mask agnostic for vector integer comparison instructions ~eopxd
@ 2022-03-17 8:52 ` ~eopxd
2022-05-11 2:26 ` Weiwei Li
2022-03-17 9:08 ` [PATCH qemu v2 07/10] target/riscv: rvv: Add mask agnostic for vector floating-point instructions ~eopxd
` (3 subsequent siblings)
9 siblings, 1 reply; 22+ messages in thread
From: ~eopxd @ 2022-03-17 8:52 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Frank Chang,
WeiWei Li, eop Chen
From: Yueh-Ting (eop) Chen <eop.chen@sifive.com>
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/vector_helper.c | 26 ++++++++++++++++----------
1 file changed, 16 insertions(+), 10 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 9bb259586d..4e48c92617 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -2131,10 +2131,12 @@ static inline void
vext_vv_rm_1(void *vd, void *v0, void *vs1, void *vs2,
CPURISCVState *env,
uint32_t vl, uint32_t vm, int vxrm,
- opivv2_rm_fn *fn)
+ opivv2_rm_fn *fn, uint32_t vma, uint32_t esz)
{
for (uint32_t i = env->vstart; i < vl; i++) {
if (!vm && !vext_elem_mask(v0, i)) {
+ /* set masked-off elements to 1s */
+ vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz);
continue;
}
fn(vd, vs1, vs2, i, env, vxrm);
@@ -2152,23 +2154,24 @@ vext_vv_rm_2(void *vd, void *v0, void *vs1, void *vs2,
uint32_t vl = env->vl;
uint32_t total_elems = vext_get_total_elems(env, desc, esz);
uint32_t vta = vext_vta(desc);
+ uint32_t vma = vext_vma(desc);
switch (env->vxrm) {
case 0: /* rnu */
vext_vv_rm_1(vd, v0, vs1, vs2,
- env, vl, vm, 0, fn);
+ env, vl, vm, 0, fn, vma, esz);
break;
case 1: /* rne */
vext_vv_rm_1(vd, v0, vs1, vs2,
- env, vl, vm, 1, fn);
+ env, vl, vm, 1, fn, vma, esz);
break;
case 2: /* rdn */
vext_vv_rm_1(vd, v0, vs1, vs2,
- env, vl, vm, 2, fn);
+ env, vl, vm, 2, fn, vma, esz);
break;
default: /* rod */
vext_vv_rm_1(vd, v0, vs1, vs2,
- env, vl, vm, 3, fn);
+ env, vl, vm, 3, fn, vma, esz);
break;
}
/* set tail elements to 1s */
@@ -2252,10 +2255,12 @@ static inline void
vext_vx_rm_1(void *vd, void *v0, target_long s1, void *vs2,
CPURISCVState *env,
uint32_t vl, uint32_t vm, int vxrm,
- opivx2_rm_fn *fn)
+ opivx2_rm_fn *fn, uint32_t vma, uint32_t esz)
{
for (uint32_t i = env->vstart; i < vl; i++) {
if (!vm && !vext_elem_mask(v0, i)) {
+ /* set masked-off elements to 1s */
+ vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz);
continue;
}
fn(vd, s1, vs2, i, env, vxrm);
@@ -2273,23 +2278,24 @@ vext_vx_rm_2(void *vd, void *v0, target_long s1, void *vs2,
uint32_t vl = env->vl;
uint32_t total_elems = vext_get_total_elems(env, desc, esz);
uint32_t vta = vext_vta(desc);
+ uint32_t vma = vext_vma(desc);
switch (env->vxrm) {
case 0: /* rnu */
vext_vx_rm_1(vd, v0, s1, vs2,
- env, vl, vm, 0, fn);
+ env, vl, vm, 0, fn, vma, esz);
break;
case 1: /* rne */
vext_vx_rm_1(vd, v0, s1, vs2,
- env, vl, vm, 1, fn);
+ env, vl, vm, 1, fn, vma, esz);
break;
case 2: /* rdn */
vext_vx_rm_1(vd, v0, s1, vs2,
- env, vl, vm, 2, fn);
+ env, vl, vm, 2, fn, vma, esz);
break;
default: /* rod */
vext_vx_rm_1(vd, v0, s1, vs2,
- env, vl, vm, 3, fn);
+ env, vl, vm, 3, fn, vma, esz);
break;
}
/* set tail elements to 1s */
--
2.34.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH qemu v2 06/10] target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic instructions
2022-03-17 8:52 ` [PATCH qemu v2 06/10] target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic instructions ~eopxd
@ 2022-05-11 2:26 ` Weiwei Li
0 siblings, 0 replies; 22+ messages in thread
From: Weiwei Li @ 2022-05-11 2:26 UTC (permalink / raw)
To: ~eopxd, qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Frank Chang,
WeiWei Li, eop Chen
在 2022/3/17 下午4:52, ~eopxd 写道:
> From: Yueh-Ting (eop) Chen <eop.chen@sifive.com>
>
> Signed-off-by: eop Chen <eop.chen@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/vector_helper.c | 26 ++++++++++++++++----------
> 1 file changed, 16 insertions(+), 10 deletions(-)
Reviewed-by: Weiwei Li<liweiwei@iscas.ac.cn>
Regards,
Weiwei Li
>
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 9bb259586d..4e48c92617 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -2131,10 +2131,12 @@ static inline void
> vext_vv_rm_1(void *vd, void *v0, void *vs1, void *vs2,
> CPURISCVState *env,
> uint32_t vl, uint32_t vm, int vxrm,
> - opivv2_rm_fn *fn)
> + opivv2_rm_fn *fn, uint32_t vma, uint32_t esz)
> {
> for (uint32_t i = env->vstart; i < vl; i++) {
> if (!vm && !vext_elem_mask(v0, i)) {
> + /* set masked-off elements to 1s */
> + vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz);
> continue;
> }
> fn(vd, vs1, vs2, i, env, vxrm);
> @@ -2152,23 +2154,24 @@ vext_vv_rm_2(void *vd, void *v0, void *vs1, void *vs2,
> uint32_t vl = env->vl;
> uint32_t total_elems = vext_get_total_elems(env, desc, esz);
> uint32_t vta = vext_vta(desc);
> + uint32_t vma = vext_vma(desc);
>
> switch (env->vxrm) {
> case 0: /* rnu */
> vext_vv_rm_1(vd, v0, vs1, vs2,
> - env, vl, vm, 0, fn);
> + env, vl, vm, 0, fn, vma, esz);
> break;
> case 1: /* rne */
> vext_vv_rm_1(vd, v0, vs1, vs2,
> - env, vl, vm, 1, fn);
> + env, vl, vm, 1, fn, vma, esz);
> break;
> case 2: /* rdn */
> vext_vv_rm_1(vd, v0, vs1, vs2,
> - env, vl, vm, 2, fn);
> + env, vl, vm, 2, fn, vma, esz);
> break;
> default: /* rod */
> vext_vv_rm_1(vd, v0, vs1, vs2,
> - env, vl, vm, 3, fn);
> + env, vl, vm, 3, fn, vma, esz);
> break;
> }
> /* set tail elements to 1s */
> @@ -2252,10 +2255,12 @@ static inline void
> vext_vx_rm_1(void *vd, void *v0, target_long s1, void *vs2,
> CPURISCVState *env,
> uint32_t vl, uint32_t vm, int vxrm,
> - opivx2_rm_fn *fn)
> + opivx2_rm_fn *fn, uint32_t vma, uint32_t esz)
> {
> for (uint32_t i = env->vstart; i < vl; i++) {
> if (!vm && !vext_elem_mask(v0, i)) {
> + /* set masked-off elements to 1s */
> + vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz);
> continue;
> }
> fn(vd, s1, vs2, i, env, vxrm);
> @@ -2273,23 +2278,24 @@ vext_vx_rm_2(void *vd, void *v0, target_long s1, void *vs2,
> uint32_t vl = env->vl;
> uint32_t total_elems = vext_get_total_elems(env, desc, esz);
> uint32_t vta = vext_vta(desc);
> + uint32_t vma = vext_vma(desc);
>
> switch (env->vxrm) {
> case 0: /* rnu */
> vext_vx_rm_1(vd, v0, s1, vs2,
> - env, vl, vm, 0, fn);
> + env, vl, vm, 0, fn, vma, esz);
> break;
> case 1: /* rne */
> vext_vx_rm_1(vd, v0, s1, vs2,
> - env, vl, vm, 1, fn);
> + env, vl, vm, 1, fn, vma, esz);
> break;
> case 2: /* rdn */
> vext_vx_rm_1(vd, v0, s1, vs2,
> - env, vl, vm, 2, fn);
> + env, vl, vm, 2, fn, vma, esz);
> break;
> default: /* rod */
> vext_vx_rm_1(vd, v0, s1, vs2,
> - env, vl, vm, 3, fn);
> + env, vl, vm, 3, fn, vma, esz);
> break;
> }
> /* set tail elements to 1s */
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH qemu v2 07/10] target/riscv: rvv: Add mask agnostic for vector floating-point instructions
2022-05-10 18:26 [PATCH qemu v2 00/10] Add mask agnostic behavior for rvv instructions ~eopxd
` (5 preceding siblings ...)
2022-03-17 8:52 ` [PATCH qemu v2 06/10] target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic instructions ~eopxd
@ 2022-03-17 9:08 ` ~eopxd
2022-05-11 2:28 ` Weiwei Li
2022-03-17 9:14 ` [PATCH qemu v2 08/10] target/riscv: rvv: Add mask agnostic for vector mask instructions ~eopxd
` (2 subsequent siblings)
9 siblings, 1 reply; 22+ messages in thread
From: ~eopxd @ 2022-03-17 9:08 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Frank Chang,
WeiWei Li, eop Chen
From: Yueh-Ting (eop) Chen <eop.chen@sifive.com>
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 12 ++++++++++++
target/riscv/vector_helper.c | 26 +++++++++++++++++++++++++
2 files changed, 38 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 5cbf323c18..8fb8045957 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2428,6 +2428,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
data = FIELD_DP32(data, VDATA, VTA, s->vta); \
data = \
FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);\
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, \
@@ -2513,6 +2514,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
data = FIELD_DP32(data, VDATA, VTA, s->vta); \
data = FIELD_DP32(data, VDATA, VTA_ALL_1S, \
s->cfg_vta_all_1s); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
fns[s->sew - 1], s); \
} \
@@ -2552,6 +2554,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, \
@@ -2592,6 +2595,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
fns[s->sew - 1], s); \
} \
@@ -2629,6 +2633,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, \
@@ -2669,6 +2674,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
fns[s->sew - 1], s); \
} \
@@ -2753,6 +2759,7 @@ static bool do_opfv(DisasContext *s, arg_rmr *a,
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
vreg_ofs(s, a->rs2), cpu_env,
s->cfg_ptr->vlen / 8,
@@ -2867,6 +2874,7 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
TCGv_i32 desc;
uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
static gen_helper_vmv_vx * const fns[3] = {
gen_helper_vmv_v_x_h,
gen_helper_vmv_v_x_w,
@@ -2968,6 +2976,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs2), cpu_env, \
s->cfg_ptr->vlen / 8, \
@@ -3021,6 +3030,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs2), cpu_env, \
s->cfg_ptr->vlen / 8, \
@@ -3089,6 +3099,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs2), cpu_env, \
s->cfg_ptr->vlen / 8, \
@@ -3144,6 +3155,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs2), cpu_env, \
s->cfg_ptr->vlen / 8, \
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 4e48c92617..5b9d766e0e 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -3053,10 +3053,14 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
uint32_t total_elems = \
vext_get_total_elems(env, desc, ESZ); \
uint32_t vta = vext_vta(desc); \
+ uint32_t vma = vext_vma(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
if (!vm && !vext_elem_mask(v0, i)) { \
+ /* set masked-off elements to 1s */ \
+ vext_set_elems_1s(vd, vma, i * ESZ, \
+ (i + 1) * ESZ); \
continue; \
} \
do_##NAME(vd, vs1, vs2, i, env); \
@@ -3092,10 +3096,14 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, \
uint32_t total_elems = \
vext_get_total_elems(env, desc, ESZ); \
uint32_t vta = vext_vta(desc); \
+ uint32_t vma = vext_vma(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
if (!vm && !vext_elem_mask(v0, i)) { \
+ /* set masked-off elements to 1s */ \
+ vext_set_elems_1s(vd, vma, i * ESZ, \
+ (i + 1) * ESZ); \
continue; \
} \
do_##NAME(vd, s1, vs2, i, env); \
@@ -3667,6 +3675,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, \
uint32_t total_elems = \
vext_get_total_elems(env, desc, ESZ); \
uint32_t vta = vext_vta(desc); \
+ uint32_t vma = vext_vma(desc); \
uint32_t i; \
\
if (vl == 0) { \
@@ -3674,6 +3683,9 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, \
} \
for (i = env->vstart; i < vl; i++) { \
if (!vm && !vext_elem_mask(v0, i)) { \
+ /* set masked-off elements to 1s */ \
+ vext_set_elems_1s(vd, vma, i * ESZ, \
+ (i + 1) * ESZ); \
continue; \
} \
do_##NAME(vd, vs2, i, env); \
@@ -4184,12 +4196,17 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
uint32_t vl = env->vl; \
uint32_t total_elems = env_archcpu(env)->cfg.vlen; \
uint32_t vta_all_1s = vext_vta_all_1s(desc); \
+ uint32_t vma = vext_vma(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
if (!vm && !vext_elem_mask(v0, i)) { \
+ /* set masked-off elements to 1s */ \
+ if (vma) { \
+ vext_set_elem_mask(vd, i, 1); \
+ } \
continue; \
} \
vext_set_elem_mask(vd, i, \
@@ -4217,11 +4234,16 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
uint32_t vl = env->vl; \
uint32_t total_elems = env_archcpu(env)->cfg.vlen; \
uint32_t vta_all_1s = vext_vta_all_1s(desc); \
+ uint32_t vma = vext_vma(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
if (!vm && !vext_elem_mask(v0, i)) { \
+ /* set masked-off elements to 1s */ \
+ if (vma) { \
+ vext_set_elem_mask(vd, i, 1); \
+ } \
continue; \
} \
vext_set_elem_mask(vd, i, \
@@ -4344,10 +4366,14 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, \
uint32_t total_elems = \
vext_get_total_elems(env, desc, ESZ); \
uint32_t vta = vext_vta(desc); \
+ uint32_t vma = vext_vma(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
if (!vm && !vext_elem_mask(v0, i)) { \
+ /* set masked-off elements to 1s */ \
+ vext_set_elems_1s(vd, vma, i * ESZ, \
+ (i + 1) * ESZ); \
continue; \
} \
do_##NAME(vd, vs2, i); \
--
2.34.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH qemu v2 07/10] target/riscv: rvv: Add mask agnostic for vector floating-point instructions
2022-03-17 9:08 ` [PATCH qemu v2 07/10] target/riscv: rvv: Add mask agnostic for vector floating-point instructions ~eopxd
@ 2022-05-11 2:28 ` Weiwei Li
0 siblings, 0 replies; 22+ messages in thread
From: Weiwei Li @ 2022-05-11 2:28 UTC (permalink / raw)
To: ~eopxd, qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Frank Chang,
WeiWei Li, eop Chen
在 2022/3/17 下午5:08, ~eopxd 写道:
> From: Yueh-Ting (eop) Chen <eop.chen@sifive.com>
>
> Signed-off-by: eop Chen <eop.chen@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 12 ++++++++++++
> target/riscv/vector_helper.c | 26 +++++++++++++++++++++++++
> 2 files changed, 38 insertions(+)
Reviewed-by: Weiwei Li<liweiwei@iscas.ac.cn>
Regards,
Weiwei Li
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 5cbf323c18..8fb8045957 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -2428,6 +2428,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
> data = FIELD_DP32(data, VDATA, VTA, s->vta); \
> data = \
> FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);\
> + data = FIELD_DP32(data, VDATA, VMA, s->vma); \
> tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
> vreg_ofs(s, a->rs1), \
> vreg_ofs(s, a->rs2), cpu_env, \
> @@ -2513,6 +2514,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
> data = FIELD_DP32(data, VDATA, VTA, s->vta); \
> data = FIELD_DP32(data, VDATA, VTA_ALL_1S, \
> s->cfg_vta_all_1s); \
> + data = FIELD_DP32(data, VDATA, VMA, s->vma); \
> return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
> fns[s->sew - 1], s); \
> } \
> @@ -2552,6 +2554,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
> data = FIELD_DP32(data, VDATA, VM, a->vm); \
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
> data = FIELD_DP32(data, VDATA, VTA, s->vta); \
> + data = FIELD_DP32(data, VDATA, VMA, s->vma); \
> tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
> vreg_ofs(s, a->rs1), \
> vreg_ofs(s, a->rs2), cpu_env, \
> @@ -2592,6 +2595,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
> data = FIELD_DP32(data, VDATA, VM, a->vm); \
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
> data = FIELD_DP32(data, VDATA, VTA, s->vta); \
> + data = FIELD_DP32(data, VDATA, VMA, s->vma); \
> return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
> fns[s->sew - 1], s); \
> } \
> @@ -2629,6 +2633,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
> data = FIELD_DP32(data, VDATA, VM, a->vm); \
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
> data = FIELD_DP32(data, VDATA, VTA, s->vta); \
> + data = FIELD_DP32(data, VDATA, VMA, s->vma); \
> tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
> vreg_ofs(s, a->rs1), \
> vreg_ofs(s, a->rs2), cpu_env, \
> @@ -2669,6 +2674,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
> data = FIELD_DP32(data, VDATA, VM, a->vm); \
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
> data = FIELD_DP32(data, VDATA, VTA, s->vta); \
> + data = FIELD_DP32(data, VDATA, VMA, s->vma); \
> return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
> fns[s->sew - 1], s); \
> } \
> @@ -2753,6 +2759,7 @@ static bool do_opfv(DisasContext *s, arg_rmr *a,
> data = FIELD_DP32(data, VDATA, VM, a->vm);
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> data = FIELD_DP32(data, VDATA, VTA, s->vta);
> + data = FIELD_DP32(data, VDATA, VMA, s->vma);
> tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
> vreg_ofs(s, a->rs2), cpu_env,
> s->cfg_ptr->vlen / 8,
> @@ -2867,6 +2874,7 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
> TCGv_i32 desc;
> uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
> data = FIELD_DP32(data, VDATA, VTA, s->vta);
> + data = FIELD_DP32(data, VDATA, VMA, s->vma);
> static gen_helper_vmv_vx * const fns[3] = {
> gen_helper_vmv_v_x_h,
> gen_helper_vmv_v_x_w,
> @@ -2968,6 +2976,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
> data = FIELD_DP32(data, VDATA, VM, a->vm); \
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
> data = FIELD_DP32(data, VDATA, VTA, s->vta); \
> + data = FIELD_DP32(data, VDATA, VMA, s->vma); \
> tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
> vreg_ofs(s, a->rs2), cpu_env, \
> s->cfg_ptr->vlen / 8, \
> @@ -3021,6 +3030,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
> data = FIELD_DP32(data, VDATA, VM, a->vm); \
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
> data = FIELD_DP32(data, VDATA, VTA, s->vta); \
> + data = FIELD_DP32(data, VDATA, VMA, s->vma); \
> tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
> vreg_ofs(s, a->rs2), cpu_env, \
> s->cfg_ptr->vlen / 8, \
> @@ -3089,6 +3099,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
> data = FIELD_DP32(data, VDATA, VM, a->vm); \
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
> data = FIELD_DP32(data, VDATA, VTA, s->vta); \
> + data = FIELD_DP32(data, VDATA, VMA, s->vma); \
> tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
> vreg_ofs(s, a->rs2), cpu_env, \
> s->cfg_ptr->vlen / 8, \
> @@ -3144,6 +3155,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
> data = FIELD_DP32(data, VDATA, VM, a->vm); \
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
> data = FIELD_DP32(data, VDATA, VTA, s->vta); \
> + data = FIELD_DP32(data, VDATA, VMA, s->vma); \
> tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
> vreg_ofs(s, a->rs2), cpu_env, \
> s->cfg_ptr->vlen / 8, \
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 4e48c92617..5b9d766e0e 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -3053,10 +3053,14 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
> uint32_t total_elems = \
> vext_get_total_elems(env, desc, ESZ); \
> uint32_t vta = vext_vta(desc); \
> + uint32_t vma = vext_vma(desc); \
> uint32_t i; \
> \
> for (i = env->vstart; i < vl; i++) { \
> if (!vm && !vext_elem_mask(v0, i)) { \
> + /* set masked-off elements to 1s */ \
> + vext_set_elems_1s(vd, vma, i * ESZ, \
> + (i + 1) * ESZ); \
> continue; \
> } \
> do_##NAME(vd, vs1, vs2, i, env); \
> @@ -3092,10 +3096,14 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, \
> uint32_t total_elems = \
> vext_get_total_elems(env, desc, ESZ); \
> uint32_t vta = vext_vta(desc); \
> + uint32_t vma = vext_vma(desc); \
> uint32_t i; \
> \
> for (i = env->vstart; i < vl; i++) { \
> if (!vm && !vext_elem_mask(v0, i)) { \
> + /* set masked-off elements to 1s */ \
> + vext_set_elems_1s(vd, vma, i * ESZ, \
> + (i + 1) * ESZ); \
> continue; \
> } \
> do_##NAME(vd, s1, vs2, i, env); \
> @@ -3667,6 +3675,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, \
> uint32_t total_elems = \
> vext_get_total_elems(env, desc, ESZ); \
> uint32_t vta = vext_vta(desc); \
> + uint32_t vma = vext_vma(desc); \
> uint32_t i; \
> \
> if (vl == 0) { \
> @@ -3674,6 +3683,9 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, \
> } \
> for (i = env->vstart; i < vl; i++) { \
> if (!vm && !vext_elem_mask(v0, i)) { \
> + /* set masked-off elements to 1s */ \
> + vext_set_elems_1s(vd, vma, i * ESZ, \
> + (i + 1) * ESZ); \
> continue; \
> } \
> do_##NAME(vd, vs2, i, env); \
> @@ -4184,12 +4196,17 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
> uint32_t vl = env->vl; \
> uint32_t total_elems = env_archcpu(env)->cfg.vlen; \
> uint32_t vta_all_1s = vext_vta_all_1s(desc); \
> + uint32_t vma = vext_vma(desc); \
> uint32_t i; \
> \
> for (i = env->vstart; i < vl; i++) { \
> ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
> ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
> if (!vm && !vext_elem_mask(v0, i)) { \
> + /* set masked-off elements to 1s */ \
> + if (vma) { \
> + vext_set_elem_mask(vd, i, 1); \
> + } \
> continue; \
> } \
> vext_set_elem_mask(vd, i, \
> @@ -4217,11 +4234,16 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
> uint32_t vl = env->vl; \
> uint32_t total_elems = env_archcpu(env)->cfg.vlen; \
> uint32_t vta_all_1s = vext_vta_all_1s(desc); \
> + uint32_t vma = vext_vma(desc); \
> uint32_t i; \
> \
> for (i = env->vstart; i < vl; i++) { \
> ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
> if (!vm && !vext_elem_mask(v0, i)) { \
> + /* set masked-off elements to 1s */ \
> + if (vma) { \
> + vext_set_elem_mask(vd, i, 1); \
> + } \
> continue; \
> } \
> vext_set_elem_mask(vd, i, \
> @@ -4344,10 +4366,14 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, \
> uint32_t total_elems = \
> vext_get_total_elems(env, desc, ESZ); \
> uint32_t vta = vext_vta(desc); \
> + uint32_t vma = vext_vma(desc); \
> uint32_t i; \
> \
> for (i = env->vstart; i < vl; i++) { \
> if (!vm && !vext_elem_mask(v0, i)) { \
> + /* set masked-off elements to 1s */ \
> + vext_set_elems_1s(vd, vma, i * ESZ, \
> + (i + 1) * ESZ); \
> continue; \
> } \
> do_##NAME(vd, vs2, i); \
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH qemu v2 08/10] target/riscv: rvv: Add mask agnostic for vector mask instructions
2022-05-10 18:26 [PATCH qemu v2 00/10] Add mask agnostic behavior for rvv instructions ~eopxd
` (6 preceding siblings ...)
2022-03-17 9:08 ` [PATCH qemu v2 07/10] target/riscv: rvv: Add mask agnostic for vector floating-point instructions ~eopxd
@ 2022-03-17 9:14 ` ~eopxd
2022-05-11 2:37 ` Weiwei Li
2022-03-17 9:32 ` [PATCH qemu v2 09/10] target/riscv: rvv: Add mask agnostic for vector permutation instructions ~eopxd
2022-05-10 18:10 ` [PATCH qemu v2 10/10] target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask agnostic behavior ~eopxd
9 siblings, 1 reply; 22+ messages in thread
From: ~eopxd @ 2022-03-17 9:14 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Frank Chang,
WeiWei Li, eop Chen
From: Yueh-Ting (eop) Chen <eop.chen@sifive.com>
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 3 +++
target/riscv/vector_helper.c | 11 +++++++++++
2 files changed, 14 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 8fb8045957..18ef9949ad 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -3352,6 +3352,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
data = \
FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);\
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), \
vreg_ofs(s, 0), vreg_ofs(s, a->rs2), \
cpu_env, s->cfg_ptr->vlen / 8, \
@@ -3390,6 +3391,7 @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
static gen_helper_gvec_3_ptr * const fns[4] = {
gen_helper_viota_m_b, gen_helper_viota_m_h,
gen_helper_viota_m_w, gen_helper_viota_m_d,
@@ -3420,6 +3422,7 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
static gen_helper_gvec_2_ptr * const fns[4] = {
gen_helper_vid_v_b, gen_helper_vid_v_h,
gen_helper_vid_v_w, gen_helper_vid_v_d,
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 5b9d766e0e..8f95e286e8 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4881,11 +4881,16 @@ static void vmsetm(void *vd, void *v0, void *vs2, CPURISCVState *env,
uint32_t vl = env->vl;
uint32_t total_elems = env_archcpu(env)->cfg.vlen;
uint32_t vta_all_1s = vext_vta_all_1s(desc);
+ uint32_t vma = vext_vma(desc);
int i;
bool first_mask_bit = false;
for (i = env->vstart; i < vl; i++) {
if (!vm && !vext_elem_mask(v0, i)) {
+ /* set masked-off elements to 1s */
+ if (vma) {
+ vext_set_elem_mask(vd, i, 1);
+ }
continue;
}
/* write a zero to all following active elements */
@@ -4946,11 +4951,14 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, CPURISCVState *env, \
uint32_t esz = sizeof(ETYPE); \
uint32_t total_elems = vext_get_total_elems(env, desc, esz); \
uint32_t vta = vext_vta(desc); \
+ uint32_t vma = vext_vma(desc); \
uint32_t sum = 0; \
int i; \
\
for (i = env->vstart; i < vl; i++) { \
if (!vm && !vext_elem_mask(v0, i)) { \
+ /* set masked-off elements to 1s */ \
+ vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); \
continue; \
} \
*((ETYPE *)vd + H(i)) = sum; \
@@ -4977,10 +4985,13 @@ void HELPER(NAME)(void *vd, void *v0, CPURISCVState *env, uint32_t desc) \
uint32_t esz = sizeof(ETYPE); \
uint32_t total_elems = vext_get_total_elems(env, desc, esz); \
uint32_t vta = vext_vta(desc); \
+ uint32_t vma = vext_vma(desc); \
int i; \
\
for (i = env->vstart; i < vl; i++) { \
if (!vm && !vext_elem_mask(v0, i)) { \
+ /* set masked-off elements to 1s */ \
+ vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); \
continue; \
} \
*((ETYPE *)vd + H(i)) = i; \
--
2.34.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH qemu v2 08/10] target/riscv: rvv: Add mask agnostic for vector mask instructions
2022-03-17 9:14 ` [PATCH qemu v2 08/10] target/riscv: rvv: Add mask agnostic for vector mask instructions ~eopxd
@ 2022-05-11 2:37 ` Weiwei Li
0 siblings, 0 replies; 22+ messages in thread
From: Weiwei Li @ 2022-05-11 2:37 UTC (permalink / raw)
To: ~eopxd, qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Frank Chang,
WeiWei Li, eop Chen
在 2022/3/17 下午5:14, ~eopxd 写道:
> From: Yueh-Ting (eop) Chen <eop.chen@sifive.com>
>
> Signed-off-by: eop Chen <eop.chen@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 3 +++
> target/riscv/vector_helper.c | 11 +++++++++++
> 2 files changed, 14 insertions(+)
Reviewed-by: Weiwei Li<liweiwei@iscas.ac.cn>
Regards,
Weiwei Li
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 8fb8045957..18ef9949ad 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -3352,6 +3352,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
> data = \
> FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);\
> + data = FIELD_DP32(data, VDATA, VMA, s->vma); \
> tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), \
> vreg_ofs(s, 0), vreg_ofs(s, a->rs2), \
> cpu_env, s->cfg_ptr->vlen / 8, \
> @@ -3390,6 +3391,7 @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
> data = FIELD_DP32(data, VDATA, VM, a->vm);
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> data = FIELD_DP32(data, VDATA, VTA, s->vta);
> + data = FIELD_DP32(data, VDATA, VMA, s->vma);
> static gen_helper_gvec_3_ptr * const fns[4] = {
> gen_helper_viota_m_b, gen_helper_viota_m_h,
> gen_helper_viota_m_w, gen_helper_viota_m_d,
> @@ -3420,6 +3422,7 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
> data = FIELD_DP32(data, VDATA, VM, a->vm);
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> data = FIELD_DP32(data, VDATA, VTA, s->vta);
> + data = FIELD_DP32(data, VDATA, VMA, s->vma);
> static gen_helper_gvec_2_ptr * const fns[4] = {
> gen_helper_vid_v_b, gen_helper_vid_v_h,
> gen_helper_vid_v_w, gen_helper_vid_v_d,
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 5b9d766e0e..8f95e286e8 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -4881,11 +4881,16 @@ static void vmsetm(void *vd, void *v0, void *vs2, CPURISCVState *env,
> uint32_t vl = env->vl;
> uint32_t total_elems = env_archcpu(env)->cfg.vlen;
> uint32_t vta_all_1s = vext_vta_all_1s(desc);
> + uint32_t vma = vext_vma(desc);
> int i;
> bool first_mask_bit = false;
>
> for (i = env->vstart; i < vl; i++) {
> if (!vm && !vext_elem_mask(v0, i)) {
> + /* set masked-off elements to 1s */
> + if (vma) {
> + vext_set_elem_mask(vd, i, 1);
> + }
> continue;
> }
> /* write a zero to all following active elements */
> @@ -4946,11 +4951,14 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, CPURISCVState *env, \
> uint32_t esz = sizeof(ETYPE); \
> uint32_t total_elems = vext_get_total_elems(env, desc, esz); \
> uint32_t vta = vext_vta(desc); \
> + uint32_t vma = vext_vma(desc); \
> uint32_t sum = 0; \
> int i; \
> \
> for (i = env->vstart; i < vl; i++) { \
> if (!vm && !vext_elem_mask(v0, i)) { \
> + /* set masked-off elements to 1s */ \
> + vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); \
> continue; \
> } \
> *((ETYPE *)vd + H(i)) = sum; \
> @@ -4977,10 +4985,13 @@ void HELPER(NAME)(void *vd, void *v0, CPURISCVState *env, uint32_t desc) \
> uint32_t esz = sizeof(ETYPE); \
> uint32_t total_elems = vext_get_total_elems(env, desc, esz); \
> uint32_t vta = vext_vta(desc); \
> + uint32_t vma = vext_vma(desc); \
> int i; \
> \
> for (i = env->vstart; i < vl; i++) { \
> if (!vm && !vext_elem_mask(v0, i)) { \
> + /* set masked-off elements to 1s */ \
> + vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); \
> continue; \
> } \
> *((ETYPE *)vd + H(i)) = i; \
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH qemu v2 09/10] target/riscv: rvv: Add mask agnostic for vector permutation instructions
2022-05-10 18:26 [PATCH qemu v2 00/10] Add mask agnostic behavior for rvv instructions ~eopxd
` (7 preceding siblings ...)
2022-03-17 9:14 ` [PATCH qemu v2 08/10] target/riscv: rvv: Add mask agnostic for vector mask instructions ~eopxd
@ 2022-03-17 9:32 ` ~eopxd
2022-05-11 2:38 ` Weiwei Li
2022-05-10 18:10 ` [PATCH qemu v2 10/10] target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask agnostic behavior ~eopxd
9 siblings, 1 reply; 22+ messages in thread
From: ~eopxd @ 2022-03-17 9:32 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Frank Chang,
WeiWei Li, eop Chen
From: Yueh-Ting (eop) Chen <eop.chen@sifive.com>
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 1 +
target/riscv/vector_helper.c | 26 +++++++++++++++++++++++--
2 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 18ef9949ad..d853f9f2c4 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -3988,6 +3988,7 @@ static bool int_ext_op(DisasContext *s, arg_rmr *a, uint8_t seq)
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
vreg_ofs(s, a->rs2), cpu_env,
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 8f95e286e8..01a3317ee8 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -5020,11 +5020,14 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
uint32_t esz = sizeof(ETYPE); \
uint32_t total_elems = vext_get_total_elems(env, desc, esz); \
uint32_t vta = vext_vta(desc); \
+ uint32_t vma = vext_vma(desc); \
target_ulong offset = s1, i_min, i; \
\
i_min = MAX(env->vstart, offset); \
for (i = i_min; i < vl; i++) { \
if (!vm && !vext_elem_mask(v0, i)) { \
+ /* set masked-off elements to 1s */ \
+ vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); \
continue; \
} \
*((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i - offset)); \
@@ -5049,13 +5052,17 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
uint32_t esz = sizeof(ETYPE); \
uint32_t total_elems = vext_get_total_elems(env, desc, esz); \
uint32_t vta = vext_vta(desc); \
+ uint32_t vma = vext_vma(desc); \
target_ulong i_max, i; \
\
i_max = MAX(MIN(s1 < vlmax ? vlmax - s1 : 0, vl), env->vstart); \
for (i = env->vstart; i < i_max; ++i) { \
- if (vm || vext_elem_mask(v0, i)) { \
- *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i + s1)); \
+ if (!vm && !vext_elem_mask(v0, i)) { \
+ /* set masked-off elements to 1s */ \
+ vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); \
+ continue; \
} \
+ *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i + s1)); \
} \
\
for (i = i_max; i < vl; ++i) { \
@@ -5085,10 +5092,13 @@ static void vslide1up_##BITWIDTH(void *vd, void *v0, target_ulong s1, \
uint32_t esz = sizeof(ETYPE); \
uint32_t total_elems = vext_get_total_elems(env, desc, esz); \
uint32_t vta = vext_vta(desc); \
+ uint32_t vma = vext_vma(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
if (!vm && !vext_elem_mask(v0, i)) { \
+ /* set masked-off elements to 1s */ \
+ vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); \
continue; \
} \
if (i == 0) { \
@@ -5130,10 +5140,13 @@ static void vslide1down_##BITWIDTH(void *vd, void *v0, target_ulong s1, \
uint32_t esz = sizeof(ETYPE); \
uint32_t total_elems = vext_get_total_elems(env, desc, esz); \
uint32_t vta = vext_vta(desc); \
+ uint32_t vma = vext_vma(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
if (!vm && !vext_elem_mask(v0, i)) { \
+ /* set masked-off elements to 1s */ \
+ vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); \
continue; \
} \
if (i == vl - 1) { \
@@ -5201,11 +5214,14 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
uint32_t esz = sizeof(TS2); \
uint32_t total_elems = vext_get_total_elems(env, desc, esz); \
uint32_t vta = vext_vta(desc); \
+ uint32_t vma = vext_vma(desc); \
uint64_t index; \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
if (!vm && !vext_elem_mask(v0, i)) { \
+ /* set masked-off elements to 1s */ \
+ vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); \
continue; \
} \
index = *((TS1 *)vs1 + HS1(i)); \
@@ -5241,11 +5257,14 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
uint32_t esz = sizeof(ETYPE); \
uint32_t total_elems = vext_get_total_elems(env, desc, esz); \
uint32_t vta = vext_vta(desc); \
+ uint32_t vma = vext_vma(desc); \
uint64_t index = s1; \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
if (!vm && !vext_elem_mask(v0, i)) { \
+ /* set masked-off elements to 1s */ \
+ vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); \
continue; \
} \
if (index >= vlmax) { \
@@ -5320,10 +5339,13 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, \
uint32_t esz = sizeof(ETYPE); \
uint32_t total_elems = vext_get_total_elems(env, desc, esz); \
uint32_t vta = vext_vta(desc); \
+ uint32_t vma = vext_vma(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
if (!vm && !vext_elem_mask(v0, i)) { \
+ /* set masked-off elements to 1s */ \
+ vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); \
continue; \
} \
*((ETYPE *)vd + HD(i)) = *((DTYPE *)vs2 + HS1(i)); \
--
2.34.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH qemu v2 09/10] target/riscv: rvv: Add mask agnostic for vector permutation instructions
2022-03-17 9:32 ` [PATCH qemu v2 09/10] target/riscv: rvv: Add mask agnostic for vector permutation instructions ~eopxd
@ 2022-05-11 2:38 ` Weiwei Li
0 siblings, 0 replies; 22+ messages in thread
From: Weiwei Li @ 2022-05-11 2:38 UTC (permalink / raw)
To: ~eopxd, qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Frank Chang,
WeiWei Li, eop Chen
在 2022/3/17 下午5:32, ~eopxd 写道:
> From: Yueh-Ting (eop) Chen <eop.chen@sifive.com>
>
> Signed-off-by: eop Chen <eop.chen@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 1 +
> target/riscv/vector_helper.c | 26 +++++++++++++++++++++++--
> 2 files changed, 25 insertions(+), 2 deletions(-)
Reviewed-by: Weiwei Li<liweiwei@iscas.ac.cn>
Regards,
Weiwei Li
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 18ef9949ad..d853f9f2c4 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -3988,6 +3988,7 @@ static bool int_ext_op(DisasContext *s, arg_rmr *a, uint8_t seq)
> data = FIELD_DP32(data, VDATA, VM, a->vm);
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> data = FIELD_DP32(data, VDATA, VTA, s->vta);
> + data = FIELD_DP32(data, VDATA, VMA, s->vma);
>
> tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
> vreg_ofs(s, a->rs2), cpu_env,
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 8f95e286e8..01a3317ee8 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -5020,11 +5020,14 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
> uint32_t esz = sizeof(ETYPE); \
> uint32_t total_elems = vext_get_total_elems(env, desc, esz); \
> uint32_t vta = vext_vta(desc); \
> + uint32_t vma = vext_vma(desc); \
> target_ulong offset = s1, i_min, i; \
> \
> i_min = MAX(env->vstart, offset); \
> for (i = i_min; i < vl; i++) { \
> if (!vm && !vext_elem_mask(v0, i)) { \
> + /* set masked-off elements to 1s */ \
> + vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); \
> continue; \
> } \
> *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i - offset)); \
> @@ -5049,13 +5052,17 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
> uint32_t esz = sizeof(ETYPE); \
> uint32_t total_elems = vext_get_total_elems(env, desc, esz); \
> uint32_t vta = vext_vta(desc); \
> + uint32_t vma = vext_vma(desc); \
> target_ulong i_max, i; \
> \
> i_max = MAX(MIN(s1 < vlmax ? vlmax - s1 : 0, vl), env->vstart); \
> for (i = env->vstart; i < i_max; ++i) { \
> - if (vm || vext_elem_mask(v0, i)) { \
> - *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i + s1)); \
> + if (!vm && !vext_elem_mask(v0, i)) { \
> + /* set masked-off elements to 1s */ \
> + vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); \
> + continue; \
> } \
> + *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i + s1)); \
> } \
> \
> for (i = i_max; i < vl; ++i) { \
> @@ -5085,10 +5092,13 @@ static void vslide1up_##BITWIDTH(void *vd, void *v0, target_ulong s1, \
> uint32_t esz = sizeof(ETYPE); \
> uint32_t total_elems = vext_get_total_elems(env, desc, esz); \
> uint32_t vta = vext_vta(desc); \
> + uint32_t vma = vext_vma(desc); \
> uint32_t i; \
> \
> for (i = env->vstart; i < vl; i++) { \
> if (!vm && !vext_elem_mask(v0, i)) { \
> + /* set masked-off elements to 1s */ \
> + vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); \
> continue; \
> } \
> if (i == 0) { \
> @@ -5130,10 +5140,13 @@ static void vslide1down_##BITWIDTH(void *vd, void *v0, target_ulong s1, \
> uint32_t esz = sizeof(ETYPE); \
> uint32_t total_elems = vext_get_total_elems(env, desc, esz); \
> uint32_t vta = vext_vta(desc); \
> + uint32_t vma = vext_vma(desc); \
> uint32_t i; \
> \
> for (i = env->vstart; i < vl; i++) { \
> if (!vm && !vext_elem_mask(v0, i)) { \
> + /* set masked-off elements to 1s */ \
> + vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); \
> continue; \
> } \
> if (i == vl - 1) { \
> @@ -5201,11 +5214,14 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
> uint32_t esz = sizeof(TS2); \
> uint32_t total_elems = vext_get_total_elems(env, desc, esz); \
> uint32_t vta = vext_vta(desc); \
> + uint32_t vma = vext_vma(desc); \
> uint64_t index; \
> uint32_t i; \
> \
> for (i = env->vstart; i < vl; i++) { \
> if (!vm && !vext_elem_mask(v0, i)) { \
> + /* set masked-off elements to 1s */ \
> + vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); \
> continue; \
> } \
> index = *((TS1 *)vs1 + HS1(i)); \
> @@ -5241,11 +5257,14 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
> uint32_t esz = sizeof(ETYPE); \
> uint32_t total_elems = vext_get_total_elems(env, desc, esz); \
> uint32_t vta = vext_vta(desc); \
> + uint32_t vma = vext_vma(desc); \
> uint64_t index = s1; \
> uint32_t i; \
> \
> for (i = env->vstart; i < vl; i++) { \
> if (!vm && !vext_elem_mask(v0, i)) { \
> + /* set masked-off elements to 1s */ \
> + vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); \
> continue; \
> } \
> if (index >= vlmax) { \
> @@ -5320,10 +5339,13 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, \
> uint32_t esz = sizeof(ETYPE); \
> uint32_t total_elems = vext_get_total_elems(env, desc, esz); \
> uint32_t vta = vext_vta(desc); \
> + uint32_t vma = vext_vma(desc); \
> uint32_t i; \
> \
> for (i = env->vstart; i < vl; i++) { \
> if (!vm && !vext_elem_mask(v0, i)) { \
> + /* set masked-off elements to 1s */ \
> + vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); \
> continue; \
> } \
> *((ETYPE *)vd + HD(i)) = *((DTYPE *)vs2 + HS1(i)); \
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH qemu v2 10/10] target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask agnostic behavior
2022-05-10 18:26 [PATCH qemu v2 00/10] Add mask agnostic behavior for rvv instructions ~eopxd
` (8 preceding siblings ...)
2022-03-17 9:32 ` [PATCH qemu v2 09/10] target/riscv: rvv: Add mask agnostic for vector permutation instructions ~eopxd
@ 2022-05-10 18:10 ` ~eopxd
2022-05-11 2:39 ` Weiwei Li
9 siblings, 1 reply; 22+ messages in thread
From: ~eopxd @ 2022-05-10 18:10 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Frank Chang,
WeiWei Li, eop Chen
From: eopXD <eop.chen@sifive.com>
According to v-spec, mask agnostic behavior can be either kept as
undisturbed or set elements' bits to all 1s. To distinguish the
difference of mask policies, QEMU should be able to simulate the mask
agnostic behavior as "set mask elements' bits to all 1s".
There are multiple possibility for agnostic elements according to
v-spec. The main intent of this patch-set tries to add option that
can distinguish between mask policies. Setting agnostic elements to
all 1s allows QEMU to express this.
This commit adds option 'rvv_ma_all_1s' is added to enable the
behavior, it is default as disabled.
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 720c8b9e5c..0245844b99 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -880,6 +880,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false),
+ DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false),
DEFINE_PROP_END_OF_LIST(),
};
--
2.34.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH qemu v2 10/10] target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask agnostic behavior
2022-05-10 18:10 ` [PATCH qemu v2 10/10] target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask agnostic behavior ~eopxd
@ 2022-05-11 2:39 ` Weiwei Li
0 siblings, 0 replies; 22+ messages in thread
From: Weiwei Li @ 2022-05-11 2:39 UTC (permalink / raw)
To: ~eopxd, qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Frank Chang,
WeiWei Li, eop Chen
在 2022/5/11 上午2:10, ~eopxd 写道:
> From: eopXD <eop.chen@sifive.com>
>
> According to v-spec, mask agnostic behavior can be either kept as
> undisturbed or set elements' bits to all 1s. To distinguish the
> difference of mask policies, QEMU should be able to simulate the mask
> agnostic behavior as "set mask elements' bits to all 1s".
>
> There are multiple possibility for agnostic elements according to
> v-spec. The main intent of this patch-set tries to add option that
> can distinguish between mask policies. Setting agnostic elements to
> all 1s allows QEMU to express this.
>
> This commit adds option 'rvv_ma_all_1s' is added to enable the
> behavior, it is default as disabled.
>
> Signed-off-by: eop Chen <eop.chen@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/cpu.c | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Weiwei Li<liweiwei@iscas.ac.cn>
Regards,
Weiwei Li
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 720c8b9e5c..0245844b99 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -880,6 +880,7 @@ static Property riscv_cpu_properties[] = {
>
> DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
> DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false),
> + DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false),
> DEFINE_PROP_END_OF_LIST(),
> };
>
^ permalink raw reply [flat|nested] 22+ messages in thread