* [PATCH v2 1/8] bsd-user:Add CPU initialization and management functions
2024-07-07 19:11 [PATCH v2 0/8] ARM AArch64 Support for BSD Ajeet Singh
@ 2024-07-07 19:11 ` Ajeet Singh
2024-07-07 19:11 ` [PATCH v2 2/8] bsd-user:Add AArch64 register handling and related functions Ajeet Singh
` (7 subsequent siblings)
8 siblings, 0 replies; 13+ messages in thread
From: Ajeet Singh @ 2024-07-07 19:11 UTC (permalink / raw)
To: qemu-devel
Cc: Warner Losh, Stacey Son, Ajeet Singh, Kyle Evans, Sean Bruno,
Jessica Clarke, Richard Henderson
From: Stacey Son <sson@FreeBSD.org>
Added function to initialize ARM CPU and check if it supports 64-bit mode.
Implemented CPU loop function to handle exceptions and emulate execution of instructions.
Added function to clone CPU state to create a new thread.
Included AArch64 specific CPU functions for bsd-user to set and receive thread-local-storage
value from the tpidr_el0 register.
Introduced structure for storing CPU register states for BSD-USER.
Signed-off-by: Stacey Son <sson@FreeBSD.org>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Co-authored-by: Kyle Evans <kevans@freebsd.org>
Co-authored-by: Sean Bruno <sbruno@freebsd.org>
Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com>
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
bsd-user/aarch64/target_arch_cpu.c | 31 +++++
bsd-user/aarch64/target_arch_cpu.h | 191 +++++++++++++++++++++++++++++
bsd-user/aarch64/target_syscall.h | 51 ++++++++
3 files changed, 273 insertions(+)
create mode 100644 bsd-user/aarch64/target_arch_cpu.c
create mode 100644 bsd-user/aarch64/target_arch_cpu.h
create mode 100644 bsd-user/aarch64/target_syscall.h
diff --git a/bsd-user/aarch64/target_arch_cpu.c b/bsd-user/aarch64/target_arch_cpu.c
new file mode 100644
index 0000000000..b2fa59efaf
--- /dev/null
+++ b/bsd-user/aarch64/target_arch_cpu.c
@@ -0,0 +1,31 @@
+/*
+ * ARM AArch64 specific CPU for bsd-user
+ *
+ * Copyright (c) 2015 Stacey Son
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+#include "qemu/osdep.h"
+#include "target_arch.h"
+
+/* See cpu_set_user_tls() in arm64/arm64/vm_machdep.c */
+void target_cpu_set_tls(CPUARMState *env, target_ulong newtls)
+{
+ env->cp15.tpidr_el[0] = newtls;
+}
+
+target_ulong target_cpu_get_tls(CPUARMState *env)
+{
+ return env->cp15.tpidr_el[0];
+}
diff --git a/bsd-user/aarch64/target_arch_cpu.h b/bsd-user/aarch64/target_arch_cpu.h
new file mode 100644
index 0000000000..4e950305d3
--- /dev/null
+++ b/bsd-user/aarch64/target_arch_cpu.h
@@ -0,0 +1,191 @@
+/*
+ * ARM AArch64 cpu init and loop
+ *
+ * Copyright (c) 2015 Stacey Son
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef TARGET_ARCH_CPU_H
+#define TARGET_ARCH_CPU_H
+
+#include "target_arch.h"
+#include "target/arm/syndrome.h"
+
+#define TARGET_DEFAULT_CPU_MODEL "any"
+
+static inline void target_cpu_init(CPUARMState *env,
+ struct target_pt_regs *regs)
+{
+ int i;
+
+ if (!(arm_feature(env, ARM_FEATURE_AARCH64))) {
+ fprintf(stderr, "The selected ARM CPU does not support 64 bit mode\n");
+ exit(1);
+ }
+ for (i = 0; i < 31; i++) {
+ env->xregs[i] = regs->regs[i];
+ }
+ env->pc = regs->pc;
+ env->xregs[31] = regs->sp;
+}
+
+
+static inline void target_cpu_loop(CPUARMState *env)
+{
+ CPUState *cs = env_cpu(env);
+ int trapnr, ec, fsc, si_code, si_signo;
+ uint64_t code, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8;
+ uint32_t pstate;
+ abi_long ret;
+
+ for (;;) {
+ cpu_exec_start(cs);
+ trapnr = cpu_exec(cs);
+ cpu_exec_end(cs);
+ process_queued_cpu_work(cs);
+
+ switch (trapnr) {
+ case EXCP_SWI:
+ /* See arm64/arm64/trap.c cpu_fetch_syscall_args() */
+ code = env->xregs[8];
+ if (code == TARGET_FREEBSD_NR_syscall ||
+ code == TARGET_FREEBSD_NR___syscall) {
+ code = env->xregs[0];
+ arg1 = env->xregs[1];
+ arg2 = env->xregs[2];
+ arg3 = env->xregs[3];
+ arg4 = env->xregs[4];
+ arg5 = env->xregs[5];
+ arg6 = env->xregs[6];
+ arg7 = env->xregs[7];
+ arg8 = 0;
+ } else {
+ arg1 = env->xregs[0];
+ arg2 = env->xregs[1];
+ arg3 = env->xregs[2];
+ arg4 = env->xregs[3];
+ arg5 = env->xregs[4];
+ arg6 = env->xregs[5];
+ arg7 = env->xregs[6];
+ arg8 = env->xregs[7];
+ }
+ ret = do_freebsd_syscall(env, code, arg1, arg2, arg3,
+ arg4, arg5, arg6, arg7, arg8);
+ /*
+ * The carry bit is cleared for no error; set for error.
+ * See arm64/arm64/vm_machdep.c cpu_set_syscall_retval()
+ */
+ pstate = pstate_read(env);
+ if (ret >= 0) {
+ pstate &= ~PSTATE_C;
+ env->xregs[0] = ret;
+ } else if (ret == -TARGET_ERESTART) {
+ env->pc -= 4;
+ break;
+ } else if (ret != -TARGET_EJUSTRETURN) {
+ pstate |= PSTATE_C;
+ env->xregs[0] = -ret;
+ }
+ pstate_write(env, pstate);
+ break;
+
+ case EXCP_INTERRUPT:
+ /* Just indicate that signals should be handle ASAP. */
+ break;
+
+ case EXCP_UDEF:
+ force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPN, env->pc);
+ break;
+
+
+ case EXCP_PREFETCH_ABORT:
+ case EXCP_DATA_ABORT:
+ /* We should only arrive here with EC in {DATAABORT, INSNABORT}. */
+ ec = syn_get_ec(env->exception.syndrome);
+ assert(ec == EC_DATAABORT || ec == EC_INSNABORT);
+
+ /* Both EC have the same format for FSC, or close enough. */
+ fsc = extract32(env->exception.syndrome, 0, 6);
+ switch (fsc) {
+ case 0x04 ... 0x07: /* Translation fault, level {0-3} */
+ si_signo = TARGET_SIGSEGV;
+ si_code = TARGET_SEGV_MAPERR;
+ break;
+ case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */
+ case 0x0d ... 0x0f: /* Permission fault, level {1-3} */
+ si_signo = TARGET_SIGSEGV;
+ si_code = TARGET_SEGV_ACCERR;
+ break;
+ case 0x11: /* Synchronous Tag Check Fault */
+ si_signo = TARGET_SIGSEGV;
+ si_code = /* TARGET_SEGV_MTESERR; */ TARGET_SEGV_ACCERR;
+ break;
+ case 0x21: /* Alignment fault */
+ si_signo = TARGET_SIGBUS;
+ si_code = TARGET_BUS_ADRALN;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ force_sig_fault(si_signo, si_code, env->exception.vaddress);
+ break;
+
+ case EXCP_DEBUG:
+ case EXCP_BKPT:
+ force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->pc);
+ break;
+
+ case EXCP_ATOMIC:
+ cpu_exec_step_atomic(cs);
+ break;
+
+ case EXCP_YIELD:
+ /* nothing to do here for user-mode, just resume guest code */
+ break;
+ default:
+ fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
+ trapnr);
+ cpu_dump_state(cs, stderr, 0);
+ abort();
+ } /* switch() */
+ process_pending_signals(env);
+ /*
+ * Exception return on AArch64 always clears the exclusive
+ * monitor, so any return to running guest code implies this.
+ * A strex (successful or otherwise) also clears the monitor, so
+ * we don't need to specialcase EXCP_STREX.
+ */
+ env->exclusive_addr = -1;
+ } /* for (;;) */
+}
+
+
+/* See arm64/arm64/vm_machdep.c cpu_fork() */
+static inline void target_cpu_clone_regs(CPUARMState *env, target_ulong newsp)
+{
+ if (newsp) {
+ env->xregs[31] = newsp;
+ }
+ env->regs[0] = 0;
+ env->regs[1] = 0;
+ pstate_write(env, 0);
+}
+
+static inline void target_cpu_reset(CPUArchState *env)
+{
+}
+
+
+#endif /* TARGET_ARCH_CPU_H */
diff --git a/bsd-user/aarch64/target_syscall.h b/bsd-user/aarch64/target_syscall.h
new file mode 100644
index 0000000000..08ae913c42
--- /dev/null
+++ b/bsd-user/aarch64/target_syscall.h
@@ -0,0 +1,51 @@
+/*
+ * ARM AArch64 specific CPU for bsd-user
+ *
+ * Copyright (c) 2015 Stacey D. Son <sson at Freebsd>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef BSD_USER_AARCH64_TARGET_SYSCALL_H
+#define BSD_USER_AARCH64_TARGET_SYSCALL_H
+
+/*
+ * The aarch64 registers are named:
+ *
+ * x0 through x30 - for 64-bit-wide access (same registers)
+ * Register '31' is one of two registers depending on the instruction context:
+ * For instructions dealing with the stack, it is the stack pointer, named rsp
+ * For all other instructions, it is a "zero" register, which returns 0 when
+ * read and discards data when written - named rzr (xzr, wzr)
+ *
+ * Usage during syscall/function call:
+ * r0-r7 are used for arguments and return values
+ * For syscalls, the syscall number is in r8
+ * r9-r15 are for temporary values (may get trampled)
+ * r16-r18 are used for intra-procedure-call and platform values (avoid)
+ * The called routine is expected to preserve r19-r28
+ * r29 and r30 are used as the frame register and link register (avoid)
+ * See the ARM Procedure Call Reference for details.
+ */
+struct target_pt_regs {
+ uint64_t regs[31];
+ uint64_t sp;
+ uint64_t pc;
+ uint64_t pstate;
+};
+
+#define TARGET_HW_MACHINE "arm64"
+#define TARGET_HW_MACHINE_ARCH "aarch64"
+
+#endif /* BSD_USER_AARCH64_TARGET_SYSCALL_H */
--
2.34.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v2 2/8] bsd-user:Add AArch64 register handling and related functions
2024-07-07 19:11 [PATCH v2 0/8] ARM AArch64 Support for BSD Ajeet Singh
2024-07-07 19:11 ` [PATCH v2 1/8] bsd-user:Add CPU initialization and management functions Ajeet Singh
@ 2024-07-07 19:11 ` Ajeet Singh
2024-07-07 19:11 ` [PATCH v2 3/8] bsd-user:Add ARM AArch64 support and capabilities Ajeet Singh
` (6 subsequent siblings)
8 siblings, 0 replies; 13+ messages in thread
From: Ajeet Singh @ 2024-07-07 19:11 UTC (permalink / raw)
To: qemu-devel
Cc: Warner Losh, Stacey Son, Ajeet Singh, Jessica Clarke, Sean Bruno,
Richard Henderson
From: Stacey Son <sson@FreeBSD.org>
Added header file for managing CPU register states in FreeBSD user mode.
Introduced prototypes for setting and getting thread-local storage (TLS).
Implemented AArch64 sysarch() system call emulation and a printing function.
Added function for setting up thread upcall to add thread support to BSD-USER.
Initialized thread's register state during thread setup.
Updated ARM AArch64 VM parameter definitions for bsd-user, including address spaces for FreeBSD/arm64 and
a function for getting the stack pointer from CPU and setting a return value.
Signed-off-by: Stacey Son <sson@FreeBSD.org>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com>
Co-authored-by: Sean Bruno <sbruno@freebsd.org>
Co-authored-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
bsd-user/aarch64/target_arch.h | 28 +++++++++++
bsd-user/aarch64/target_arch_reg.h | 56 +++++++++++++++++++++
bsd-user/aarch64/target_arch_sysarch.h | 42 ++++++++++++++++
bsd-user/aarch64/target_arch_thread.h | 61 +++++++++++++++++++++++
bsd-user/aarch64/target_arch_vmparam.h | 68 ++++++++++++++++++++++++++
5 files changed, 255 insertions(+)
create mode 100644 bsd-user/aarch64/target_arch.h
create mode 100644 bsd-user/aarch64/target_arch_reg.h
create mode 100644 bsd-user/aarch64/target_arch_sysarch.h
create mode 100644 bsd-user/aarch64/target_arch_thread.h
create mode 100644 bsd-user/aarch64/target_arch_vmparam.h
diff --git a/bsd-user/aarch64/target_arch.h b/bsd-user/aarch64/target_arch.h
new file mode 100644
index 0000000000..27f47de8eb
--- /dev/null
+++ b/bsd-user/aarch64/target_arch.h
@@ -0,0 +1,28 @@
+/*
+ * ARM AArch64 specific prototypes for bsd-user
+ *
+ * Copyright (c) 2015 Stacey D. Son <sson at FreeBSD>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef TARGET_ARCH_H
+#define TARGET_ARCH_H
+
+#include "qemu.h"
+
+void target_cpu_set_tls(CPUARMState *env, target_ulong newtls);
+target_ulong target_cpu_get_tls(CPUARMState *env);
+
+#endif /* TARGET_ARCH_H */
diff --git a/bsd-user/aarch64/target_arch_reg.h b/bsd-user/aarch64/target_arch_reg.h
new file mode 100644
index 0000000000..5c7154f0c1
--- /dev/null
+++ b/bsd-user/aarch64/target_arch_reg.h
@@ -0,0 +1,56 @@
+/*
+ * FreeBSD arm64 register structures
+ *
+ * Copyright (c) 2015 Stacey Son
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef TARGET_ARCH_REG_H
+#define TARGET_ARCH_REG_H
+
+/* See sys/arm64/include/reg.h */
+typedef struct target_reg {
+ uint64_t x[30];
+ uint64_t lr;
+ uint64_t sp;
+ uint64_t elr;
+ uint64_t spsr;
+} target_reg_t;
+
+typedef struct target_fpreg {
+ __uint128_t fp_q[32];
+ uint32_t fp_sr;
+ uint32_t fp_cr;
+} target_fpreg_t;
+
+#define tswapreg(ptr) tswapal(ptr)
+
+static inline void target_copy_regs(target_reg_t *regs, CPUARMState *env)
+{
+ int i;
+
+ for (i = 0; i < 30; i++) {
+ regs->x[i] = tswapreg(env->xregs[i]);
+ }
+ regs->lr = tswapreg(env->xregs[30]);
+ regs->sp = tswapreg(env->xregs[31]);
+ regs->elr = tswapreg(env->pc);
+ regs->spsr = tswapreg(pstate_read(env));
+}
+
+#undef tswapreg
+
+#endif /* TARGET_ARCH_REG_H */
diff --git a/bsd-user/aarch64/target_arch_sysarch.h b/bsd-user/aarch64/target_arch_sysarch.h
new file mode 100644
index 0000000000..b003015daf
--- /dev/null
+++ b/bsd-user/aarch64/target_arch_sysarch.h
@@ -0,0 +1,42 @@
+/*
+ * ARM AArch64 sysarch() system call emulation for bsd-user.
+ *
+ * Copyright (c) 2015 <sson at FreeBSD>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef TARGET_ARCH_SYSARCH_H
+#define TARGET_ARCH_SYSARCH_H
+
+#include "target_syscall.h"
+#include "target_arch.h"
+
+/* See sysarch() in sys/arm64/arm64/sys_machdep.c */
+static inline abi_long do_freebsd_arch_sysarch(CPUARMState *env, int op,
+ abi_ulong parms)
+{
+ int ret = -TARGET_EOPNOTSUPP;
+
+ fprintf(stderr, "sysarch");
+ return ret;
+}
+
+static inline void do_freebsd_arch_print_sysarch(
+ const struct syscallname *name, abi_long arg1, abi_long arg2,
+ abi_long arg3, abi_long arg4, abi_long arg5, abi_long arg6)
+{
+}
+
+#endif /* TARGET_ARCH_SYSARCH_H */
diff --git a/bsd-user/aarch64/target_arch_thread.h b/bsd-user/aarch64/target_arch_thread.h
new file mode 100644
index 0000000000..4c911e605a
--- /dev/null
+++ b/bsd-user/aarch64/target_arch_thread.h
@@ -0,0 +1,61 @@
+/*
+ * ARM AArch64 thread support for bsd-user.
+ *
+ * Copyright (c) 2015 Stacey D. Son <sson at FreeBSD>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef TARGET_ARCH_THREAD_H
+#define TARGET_ARCH_THREAD_H
+
+/* Compare to arm64/arm64/vm_machdep.c cpu_set_upcall_kse() */
+static inline void target_thread_set_upcall(CPUARMState *regs, abi_ulong entry,
+ abi_ulong arg, abi_ulong stack_base, abi_ulong stack_size)
+{
+ abi_ulong sp;
+
+ /*
+ * Make sure the stack is properly aligned.
+ * arm64/include/param.h (STACKLIGN() macro)
+ */
+ sp = ROUND_DOWN(stack_base + stack_size, 16);
+
+ /* sp = stack base */
+ regs->xregs[31] = sp;
+ /* pc = start function entry */
+ regs->pc = entry;
+ /* r0 = arg */
+ regs->xregs[0] = arg;
+
+
+}
+
+static inline void target_thread_init(struct target_pt_regs *regs,
+ struct image_info *infop)
+{
+ abi_long stack = infop->start_stack;
+
+ /*
+ * Make sure the stack is properly aligned.
+ * arm64/include/param.h (STACKLIGN() macro)
+ */
+
+ memset(regs, 0, sizeof(*regs));
+ regs->regs[0] = infop->start_stack;
+ regs->pc = infop->entry;
+ regs->sp = ROUND_DOWN(stack, 16);
+}
+
+#endif /* TARGET_ARCH_THREAD_H */
diff --git a/bsd-user/aarch64/target_arch_vmparam.h b/bsd-user/aarch64/target_arch_vmparam.h
new file mode 100644
index 0000000000..dc66e1289b
--- /dev/null
+++ b/bsd-user/aarch64/target_arch_vmparam.h
@@ -0,0 +1,68 @@
+/*
+ * ARM AArch64 VM parameters definitions for bsd-user.
+ *
+ * Copyright (c) 2015 Stacey D. Son <sson at FreeBSD>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef TARGET_ARCH_VMPARAM_H
+#define TARGET_ARCH_VMPARAM_H
+
+#include "cpu.h"
+
+/**
+ * FreeBSD/arm64 Address space layout.
+ *
+ * ARMv8 implements up to a 48 bit virtual address space. The address space is
+ * split into 2 regions at each end of the 64 bit address space, with an
+ * out of range "hole" in the middle.
+ *
+ * We limit the size of the two spaces to 39 bits each.
+ *
+ * Upper region: 0xffffffffffffffff
+ * 0xffffff8000000000
+ *
+ * Hole: 0xffffff7fffffffff
+ * 0x0000008000000000
+ *
+ * Lower region: 0x0000007fffffffff
+ * 0x0000000000000000
+ *
+ * The upper region for the kernel, and the lower region for userland.
+ */
+
+
+/* compare to sys/arm64/include/vmparam.h */
+#define TARGET_MAXTSIZ (1 * GiB) /* max text size */
+#define TARGET_DFLDSIZ (128 * MiB) /* initial data size limit */
+#define TARGET_MAXDSIZ (1 * GiB) /* max data size */
+#define TARGET_DFLSSIZ (128 * MiB) /* initial stack size limit */
+#define TARGET_MAXSSIZ (1 * GiB) /* max stack size */
+#define TARGET_SGROWSIZ (128 * KiB) /* amount to grow stack */
+
+ /* KERNBASE - 512 MB */
+#define TARGET_VM_MAXUSER_ADDRESS (0x00007fffff000000ULL - (512 * MiB))
+#define TARGET_USRSTACK TARGET_VM_MAXUSER_ADDRESS
+
+static inline abi_ulong get_sp_from_cpustate(CPUARMState *state)
+{
+ return state->xregs[31]; /* sp */
+}
+
+static inline void set_second_rval(CPUARMState *state, abi_ulong retval2)
+{
+ state->xregs[1] = retval2; /* XXX not really used on 64-bit arch */
+}
+#endif /* TARGET_ARCH_VMPARAM_H */
--
2.34.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v2 3/8] bsd-user:Add ARM AArch64 support and capabilities
2024-07-07 19:11 [PATCH v2 0/8] ARM AArch64 Support for BSD Ajeet Singh
2024-07-07 19:11 ` [PATCH v2 1/8] bsd-user:Add CPU initialization and management functions Ajeet Singh
2024-07-07 19:11 ` [PATCH v2 2/8] bsd-user:Add AArch64 register handling and related functions Ajeet Singh
@ 2024-07-07 19:11 ` Ajeet Singh
2024-07-07 19:11 ` [PATCH v2 4/8] bsd-user:Add ARM AArch64 signal handling support Ajeet Singh
` (5 subsequent siblings)
8 siblings, 0 replies; 13+ messages in thread
From: Ajeet Singh @ 2024-07-07 19:11 UTC (permalink / raw)
To: qemu-devel
Cc: Warner Losh, Stacey Son, Ajeet Singh, Kyle Evans,
Richard Henderson
From: Warner Losh <imp@bsdimp.com>
Added function to access rval2 by accessing the x1 register.
Defined ARM AArch64 ELF parameters including mmap and dynamic load addresses.
Introduced extensive hardware capability definitions and macros for retrieving hardware capability (hwcap) flags.
Implemented function to retrieve ARM AArch64 hardware capabilities using the `GET_FEATURE_ID` macro.
Added function to retrieve extended ARM AArch64 hardware capability flags.
Signed-off-by: Stacey Son <sson@FreeBSD.org>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Signed-off-by: Warner Losh <imp@bsdimp.com>
Co-authored-by: Kyle Evans <kevans@FreeBSD.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
bsd-user/aarch64/target_arch_elf.h | 165 +++++++++++++++++++++++++
bsd-user/aarch64/target_arch_vmparam.h | 6 +
2 files changed, 171 insertions(+)
create mode 100644 bsd-user/aarch64/target_arch_elf.h
diff --git a/bsd-user/aarch64/target_arch_elf.h b/bsd-user/aarch64/target_arch_elf.h
new file mode 100644
index 0000000000..7202cd8334
--- /dev/null
+++ b/bsd-user/aarch64/target_arch_elf.h
@@ -0,0 +1,165 @@
+/*
+ * ARM AArch64 ELF definitions for bsd-user
+ *
+ * Copyright (c) 2015 Stacey D. Son
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef TARGET_ARCH_ELF_H
+#define TARGET_ARCH_ELF_H
+
+#include "target/arm/cpu-features.h"
+
+#define ELF_START_MMAP 0x80000000
+#define ELF_ET_DYN_LOAD_ADDR 0x100000
+
+#define elf_check_arch(x) ((x) == EM_AARCH64)
+
+#define ELF_CLASS ELFCLASS64
+#define ELF_DATA ELFDATA2LSB
+#define ELF_ARCH EM_AARCH64
+
+#define USE_ELF_CORE_DUMP
+#define ELF_EXEC_PAGESIZE 4096
+
+enum {
+ ARM_HWCAP_A64_FP = 1 << 0,
+ ARM_HWCAP_A64_ASIMD = 1 << 1,
+ ARM_HWCAP_A64_EVTSTRM = 1 << 2,
+ ARM_HWCAP_A64_AES = 1 << 3,
+ ARM_HWCAP_A64_PMULL = 1 << 4,
+ ARM_HWCAP_A64_SHA1 = 1 << 5,
+ ARM_HWCAP_A64_SHA2 = 1 << 6,
+ ARM_HWCAP_A64_CRC32 = 1 << 7,
+ ARM_HWCAP_A64_ATOMICS = 1 << 8,
+ ARM_HWCAP_A64_FPHP = 1 << 9,
+ ARM_HWCAP_A64_ASIMDHP = 1 << 10,
+ ARM_HWCAP_A64_CPUID = 1 << 11,
+ ARM_HWCAP_A64_ASIMDRDM = 1 << 12,
+ ARM_HWCAP_A64_JSCVT = 1 << 13,
+ ARM_HWCAP_A64_FCMA = 1 << 14,
+ ARM_HWCAP_A64_LRCPC = 1 << 15,
+ ARM_HWCAP_A64_DCPOP = 1 << 16,
+ ARM_HWCAP_A64_SHA3 = 1 << 17,
+ ARM_HWCAP_A64_SM3 = 1 << 18,
+ ARM_HWCAP_A64_SM4 = 1 << 19,
+ ARM_HWCAP_A64_ASIMDDP = 1 << 20,
+ ARM_HWCAP_A64_SHA512 = 1 << 21,
+ ARM_HWCAP_A64_SVE = 1 << 22,
+ ARM_HWCAP_A64_ASIMDFHM = 1 << 23,
+ ARM_HWCAP_A64_DIT = 1 << 24,
+ ARM_HWCAP_A64_USCAT = 1 << 25,
+ ARM_HWCAP_A64_ILRCPC = 1 << 26,
+ ARM_HWCAP_A64_FLAGM = 1 << 27,
+ ARM_HWCAP_A64_SSBS = 1 << 28,
+ ARM_HWCAP_A64_SB = 1 << 29,
+ ARM_HWCAP_A64_PACA = 1 << 30,
+ ARM_HWCAP_A64_PACG = 1UL << 31,
+
+ ARM_HWCAP2_A64_DCPODP = 1 << 0,
+ ARM_HWCAP2_A64_SVE2 = 1 << 1,
+ ARM_HWCAP2_A64_SVEAES = 1 << 2,
+ ARM_HWCAP2_A64_SVEPMULL = 1 << 3,
+ ARM_HWCAP2_A64_SVEBITPERM = 1 << 4,
+ ARM_HWCAP2_A64_SVESHA3 = 1 << 5,
+ ARM_HWCAP2_A64_SVESM4 = 1 << 6,
+ ARM_HWCAP2_A64_FLAGM2 = 1 << 7,
+ ARM_HWCAP2_A64_FRINT = 1 << 8,
+ ARM_HWCAP2_A64_SVEI8MM = 1 << 9,
+ ARM_HWCAP2_A64_SVEF32MM = 1 << 10,
+ ARM_HWCAP2_A64_SVEF64MM = 1 << 11,
+ ARM_HWCAP2_A64_SVEBF16 = 1 << 12,
+ ARM_HWCAP2_A64_I8MM = 1 << 13,
+ ARM_HWCAP2_A64_BF16 = 1 << 14,
+ ARM_HWCAP2_A64_DGH = 1 << 15,
+ ARM_HWCAP2_A64_RNG = 1 << 16,
+ ARM_HWCAP2_A64_BTI = 1 << 17,
+ ARM_HWCAP2_A64_MTE = 1 << 18,
+};
+
+#define ELF_HWCAP get_elf_hwcap()
+#define ELF_HWCAP2 get_elf_hwcap2()
+
+#define GET_FEATURE_ID(feat, hwcap) \
+ do { if (cpu_isar_feature(feat, cpu)) { hwcaps |= hwcap; } } while (0)
+
+static uint32_t get_elf_hwcap(void)
+{
+ ARMCPU *cpu = ARM_CPU(thread_cpu);
+ uint32_t hwcaps = 0;
+
+ hwcaps |= ARM_HWCAP_A64_FP;
+ hwcaps |= ARM_HWCAP_A64_ASIMD;
+ hwcaps |= ARM_HWCAP_A64_CPUID;
+
+ /* probe for the extra features */
+
+ GET_FEATURE_ID(aa64_aes, ARM_HWCAP_A64_AES);
+ GET_FEATURE_ID(aa64_pmull, ARM_HWCAP_A64_PMULL);
+ GET_FEATURE_ID(aa64_sha1, ARM_HWCAP_A64_SHA1);
+ GET_FEATURE_ID(aa64_sha256, ARM_HWCAP_A64_SHA2);
+ GET_FEATURE_ID(aa64_sha512, ARM_HWCAP_A64_SHA512);
+ GET_FEATURE_ID(aa64_crc32, ARM_HWCAP_A64_CRC32);
+ GET_FEATURE_ID(aa64_sha3, ARM_HWCAP_A64_SHA3);
+ GET_FEATURE_ID(aa64_sm3, ARM_HWCAP_A64_SM3);
+ GET_FEATURE_ID(aa64_sm4, ARM_HWCAP_A64_SM4);
+ GET_FEATURE_ID(aa64_fp16, ARM_HWCAP_A64_FPHP | ARM_HWCAP_A64_ASIMDHP);
+ GET_FEATURE_ID(aa64_atomics, ARM_HWCAP_A64_ATOMICS);
+ GET_FEATURE_ID(aa64_rdm, ARM_HWCAP_A64_ASIMDRDM);
+ GET_FEATURE_ID(aa64_dp, ARM_HWCAP_A64_ASIMDDP);
+ GET_FEATURE_ID(aa64_fcma, ARM_HWCAP_A64_FCMA);
+ GET_FEATURE_ID(aa64_sve, ARM_HWCAP_A64_SVE);
+ GET_FEATURE_ID(aa64_pauth, ARM_HWCAP_A64_PACA | ARM_HWCAP_A64_PACG);
+ GET_FEATURE_ID(aa64_fhm, ARM_HWCAP_A64_ASIMDFHM);
+ GET_FEATURE_ID(aa64_jscvt, ARM_HWCAP_A64_JSCVT);
+ GET_FEATURE_ID(aa64_sb, ARM_HWCAP_A64_SB);
+ GET_FEATURE_ID(aa64_condm_4, ARM_HWCAP_A64_FLAGM);
+ GET_FEATURE_ID(aa64_dcpop, ARM_HWCAP_A64_DCPOP);
+ GET_FEATURE_ID(aa64_rcpc_8_3, ARM_HWCAP_A64_LRCPC);
+ GET_FEATURE_ID(aa64_rcpc_8_4, ARM_HWCAP_A64_ILRCPC);
+
+ return hwcaps;
+}
+
+static uint32_t get_elf_hwcap2(void)
+{
+ ARMCPU *cpu = ARM_CPU(thread_cpu);
+ uint32_t hwcaps = 0;
+
+ GET_FEATURE_ID(aa64_dcpodp, ARM_HWCAP2_A64_DCPODP);
+ GET_FEATURE_ID(aa64_sve2, ARM_HWCAP2_A64_SVE2);
+ GET_FEATURE_ID(aa64_sve2_aes, ARM_HWCAP2_A64_SVEAES);
+ GET_FEATURE_ID(aa64_sve2_pmull128, ARM_HWCAP2_A64_SVEPMULL);
+ GET_FEATURE_ID(aa64_sve2_bitperm, ARM_HWCAP2_A64_SVEBITPERM);
+ GET_FEATURE_ID(aa64_sve2_sha3, ARM_HWCAP2_A64_SVESHA3);
+ GET_FEATURE_ID(aa64_sve2_sm4, ARM_HWCAP2_A64_SVESM4);
+ GET_FEATURE_ID(aa64_condm_5, ARM_HWCAP2_A64_FLAGM2);
+ GET_FEATURE_ID(aa64_frint, ARM_HWCAP2_A64_FRINT);
+ GET_FEATURE_ID(aa64_sve_i8mm, ARM_HWCAP2_A64_SVEI8MM);
+ GET_FEATURE_ID(aa64_sve_f32mm, ARM_HWCAP2_A64_SVEF32MM);
+ GET_FEATURE_ID(aa64_sve_f64mm, ARM_HWCAP2_A64_SVEF64MM);
+ GET_FEATURE_ID(aa64_sve_bf16, ARM_HWCAP2_A64_SVEBF16);
+ GET_FEATURE_ID(aa64_i8mm, ARM_HWCAP2_A64_I8MM);
+ GET_FEATURE_ID(aa64_bf16, ARM_HWCAP2_A64_BF16);
+ GET_FEATURE_ID(aa64_rndr, ARM_HWCAP2_A64_RNG);
+ GET_FEATURE_ID(aa64_bti, ARM_HWCAP2_A64_BTI);
+ GET_FEATURE_ID(aa64_mte, ARM_HWCAP2_A64_MTE);
+
+ return hwcaps;
+}
+
+#undef GET_FEATURE_ID
+
+#endif /* TARGET_ARCH_ELF_H */
diff --git a/bsd-user/aarch64/target_arch_vmparam.h b/bsd-user/aarch64/target_arch_vmparam.h
index dc66e1289b..0c35491970 100644
--- a/bsd-user/aarch64/target_arch_vmparam.h
+++ b/bsd-user/aarch64/target_arch_vmparam.h
@@ -65,4 +65,10 @@ static inline void set_second_rval(CPUARMState *state, abi_ulong retval2)
{
state->xregs[1] = retval2; /* XXX not really used on 64-bit arch */
}
+
+static inline abi_ulong get_second_rval(CPUARMState *state)
+{
+ return state->xregs[1];
+}
+
#endif /* TARGET_ARCH_VMPARAM_H */
--
2.34.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v2 4/8] bsd-user:Add ARM AArch64 signal handling support
2024-07-07 19:11 [PATCH v2 0/8] ARM AArch64 Support for BSD Ajeet Singh
` (2 preceding siblings ...)
2024-07-07 19:11 ` [PATCH v2 3/8] bsd-user:Add ARM AArch64 support and capabilities Ajeet Singh
@ 2024-07-07 19:11 ` Ajeet Singh
2024-07-07 19:11 ` [PATCH v2 5/8] bsd-user:Add get_mcontext function for ARM AArch64 Ajeet Singh
` (4 subsequent siblings)
8 siblings, 0 replies; 13+ messages in thread
From: Ajeet Singh @ 2024-07-07 19:11 UTC (permalink / raw)
To: qemu-devel; +Cc: Warner Losh, Stacey Son, Ajeet Singh, Richard Henderson
From: Stacey Son <sson@FreeBSD.org>
Added sigcode setup function for signal trampoline which initializes a sequence of instructions
to handle signal returns and exits, copying this code to the target offset.
Defined ARM AArch64 specific signal definitions including register indices and sizes,
and introduced structures to represent general purpose registers, floating point registers, and machine context.
Added function to set up signal handler arguments, populating register values in `CPUARMState`
based on the provided signal, signal frame, signal action, and frame address.
Signed-off-by: Stacey Son <sson@FreeBSD.org>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Signed-off-by: Warner Losh <imp@bsdimp.com>
Co-authored-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
bsd-user/aarch64/signal.c | 53 ++++++++++++++++
bsd-user/aarch64/target_arch_signal.h | 80 +++++++++++++++++++++++++
bsd-user/aarch64/target_arch_sigtramp.h | 48 +++++++++++++++
3 files changed, 181 insertions(+)
create mode 100644 bsd-user/aarch64/signal.c
create mode 100644 bsd-user/aarch64/target_arch_signal.h
create mode 100644 bsd-user/aarch64/target_arch_sigtramp.h
diff --git a/bsd-user/aarch64/signal.c b/bsd-user/aarch64/signal.c
new file mode 100644
index 0000000000..98861f9ab3
--- /dev/null
+++ b/bsd-user/aarch64/signal.c
@@ -0,0 +1,53 @@
+/*
+ * ARM AArch64 specific signal definitions for bsd-user
+ *
+ * Copyright (c) 2015 Stacey D. Son <sson at FreeBSD>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+#include "qemu/osdep.h"
+
+#include "qemu.h"
+
+/*
+ * Compare to sendsig() in sys/arm64/arm64/machdep.c
+ * Assumes that target stack frame memory is locked.
+ */
+abi_long set_sigtramp_args(CPUARMState *regs, int sig,
+ struct target_sigframe *frame,
+ abi_ulong frame_addr,
+ struct target_sigaction *ka)
+{
+ /*
+ * Arguments to signal handler:
+ * x0 = signal number
+ * x1 = siginfo pointer
+ * x2 = ucontext pointer
+ * pc/elr = signal handler pointer
+ * sp = sigframe struct pointer
+ * lr = sigtramp at base of user stack
+ */
+
+ regs->xregs[0] = sig;
+ regs->xregs[1] = frame_addr +
+ offsetof(struct target_sigframe, sf_si);
+ regs->xregs[2] = frame_addr +
+ offsetof(struct target_sigframe, sf_uc);
+
+ regs->pc = ka->_sa_handler;
+ regs->xregs[TARGET_REG_SP] = frame_addr;
+ regs->xregs[TARGET_REG_LR] = TARGET_PS_STRINGS - TARGET_SZSIGCODE;
+
+ return 0;
+}
diff --git a/bsd-user/aarch64/target_arch_signal.h b/bsd-user/aarch64/target_arch_signal.h
new file mode 100644
index 0000000000..df17173316
--- /dev/null
+++ b/bsd-user/aarch64/target_arch_signal.h
@@ -0,0 +1,80 @@
+/*
+ * ARM AArch64 specific signal definitions for bsd-user
+ *
+ * Copyright (c) 2015 Stacey D. Son <sson at FreeBSD>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef TARGET_ARCH_SIGNAL_H
+#define TARGET_ARCH_SIGNAL_H
+
+#include "cpu.h"
+
+#define TARGET_REG_X0 0
+#define TARGET_REG_X30 30
+#define TARGET_REG_X31 31
+#define TARGET_REG_LR TARGET_REG_X30
+#define TARGET_REG_SP TARGET_REG_X31
+
+#define TARGET_INSN_SIZE 4 /* arm64 instruction size */
+
+/* Size of the signal trampolin code. See _sigtramp(). */
+#define TARGET_SZSIGCODE ((abi_ulong)(9 * TARGET_INSN_SIZE))
+
+/* compare to sys/arm64/include/_limits.h */
+#define TARGET_MINSIGSTKSZ (1024 * 4) /* min sig stack size */
+#define TARGET_SIGSTKSZ (TARGET_MINSIGSTKSZ + 32768) /* recommended size */
+
+/* struct __mcontext in sys/arm64/include/ucontext.h */
+
+struct target_gpregs {
+ uint64_t gp_x[30];
+ uint64_t gp_lr;
+ uint64_t gp_sp;
+ uint64_t gp_elr;
+ uint32_t gp_spsr;
+ uint32_t gp_pad;
+};
+
+struct target_fpregs {
+ __uint128_t fp_q[32];
+ uint32_t fp_sr;
+ uint32_t fp_cr;
+ uint32_t fp_flags;
+ uint32_t fp_pad;
+};
+
+struct target__mcontext {
+ struct target_gpregs mc_gpregs;
+ struct target_fpregs mc_fpregs;
+ uint32_t mc_flags;
+#define TARGET_MC_FP_VALID 0x1
+ uint32_t mc_pad;
+ uint64_t mc_spare[8];
+};
+
+typedef struct target__mcontext target_mcontext_t;
+
+#define TARGET_MCONTEXT_SIZE 880
+#define TARGET_UCONTEXT_SIZE 960
+
+#include "target_os_ucontext.h"
+
+struct target_sigframe {
+ target_siginfo_t sf_si; /* saved siginfo */
+ target_ucontext_t sf_uc; /* saved ucontext */
+};
+
+#endif /* TARGET_ARCH_SIGNAL_H */
diff --git a/bsd-user/aarch64/target_arch_sigtramp.h b/bsd-user/aarch64/target_arch_sigtramp.h
new file mode 100644
index 0000000000..8cdd33b621
--- /dev/null
+++ b/bsd-user/aarch64/target_arch_sigtramp.h
@@ -0,0 +1,48 @@
+/*
+ * ARM AArch64 sigcode for bsd-user
+ *
+ * Copyright (c) 2015 Stacey D. Son <sson at FreeBSD>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef TARGET_ARCH_SIGTRAMP_H
+#define TARGET_ARCH_SIGTRAMP_H
+
+/* Compare to ENTRY(sigcode) in arm64/arm64/locore.S */
+static inline abi_long setup_sigtramp(abi_ulong offset, unsigned sigf_uc,
+ unsigned sys_sigreturn)
+{
+ int i;
+ uint32_t sys_exit = TARGET_FREEBSD_NR_exit;
+
+ uint32_t sigtramp_code[] = {
+ /* 1 */ 0x910003e0, /* mov x0, sp */
+ /* 2 */ 0x91000000 + (sigf_uc << 10), /* add x0, x0, #SIGF_UC */
+ /* 3 */ 0xd2800000 + (sys_sigreturn << 5) + 0x8, /* mov x8, #SYS_sigreturn */
+ /* 4 */ 0xd4000001, /* svc #0 */
+ /* 5 */ 0xd2800028 + (sys_exit << 5) + 0x8, /* mov x8, #SYS_exit */
+ /* 6 */ 0xd4000001, /* svc #0 */
+ /* 7 */ 0x17fffffc, /* b -4 */
+ /* 8 */ sys_sigreturn,
+ /* 9 */ sys_exit
+ };
+
+ for (i = 0; i < 9; i++) {
+ tswap32s(&sigtramp_code[i]);
+ }
+
+ return memcpy_to_target(offset, sigtramp_code, TARGET_SZSIGCODE);
+}
+#endif /* TARGET_ARCH_SIGTRAMP_H */
--
2.34.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v2 5/8] bsd-user:Add get_mcontext function for ARM AArch64
2024-07-07 19:11 [PATCH v2 0/8] ARM AArch64 Support for BSD Ajeet Singh
` (3 preceding siblings ...)
2024-07-07 19:11 ` [PATCH v2 4/8] bsd-user:Add ARM AArch64 signal handling support Ajeet Singh
@ 2024-07-07 19:11 ` Ajeet Singh
2024-07-08 16:09 ` Richard Henderson
2024-07-07 19:11 ` [PATCH v2 6/8] bsd-user:Add setup_sigframe_arch " Ajeet Singh
` (3 subsequent siblings)
8 siblings, 1 reply; 13+ messages in thread
From: Ajeet Singh @ 2024-07-07 19:11 UTC (permalink / raw)
To: qemu-devel; +Cc: Warner Losh, Stacey Son, Ajeet Singh, Kyle Evans
From: Stacey Son <sson@FreeBSD.org>
function to retrieve machine context,it populates the provided
target_mcontext_t structure with information from the CPUARMState
registers.
Signed-off-by: Stacey Son <sson@FreeBSD.org>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Co-authored-by: Kyle Evans <kevans@FreeBSD.org>
---
bsd-user/aarch64/signal.c | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/bsd-user/aarch64/signal.c b/bsd-user/aarch64/signal.c
index 98861f9ab3..ab3bf8558a 100644
--- a/bsd-user/aarch64/signal.c
+++ b/bsd-user/aarch64/signal.c
@@ -51,3 +51,33 @@ abi_long set_sigtramp_args(CPUARMState *regs, int sig,
return 0;
}
+
+/*
+ * Compare to get_mcontext() in arm64/arm64/machdep.c
+ * Assumes that the memory is locked if mcp points to user memory.
+ */
+abi_long get_mcontext(CPUARMState *regs, target_mcontext_t *mcp, int flags)
+{
+ int err = 0, i;
+ uint64_t *gr = mcp->mc_gpregs.gp_x;
+
+ mcp->mc_gpregs.gp_spsr = pstate_read(regs);
+ if (flags & TARGET_MC_GET_CLEAR_RET) {
+ gr[0] = 0UL;
+ mcp->mc_gpregs.gp_spsr &= ~CPSR_C;
+ } else {
+ gr[0] = tswap64(regs->xregs[0]);
+ }
+
+ for (i = 1; i < 30; i++) {
+ gr[i] = tswap64(regs->xregs[i]);
+ }
+
+ mcp->mc_gpregs.gp_sp = tswap64(regs->xregs[TARGET_REG_SP]);
+ mcp->mc_gpregs.gp_lr = tswap64(regs->xregs[TARGET_REG_LR]);
+ mcp->mc_gpregs.gp_elr = tswap64(regs->pc);
+
+ /* XXX FP? */
+
+ return err;
+}
--
2.34.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH v2 5/8] bsd-user:Add get_mcontext function for ARM AArch64
2024-07-07 19:11 ` [PATCH v2 5/8] bsd-user:Add get_mcontext function for ARM AArch64 Ajeet Singh
@ 2024-07-08 16:09 ` Richard Henderson
0 siblings, 0 replies; 13+ messages in thread
From: Richard Henderson @ 2024-07-08 16:09 UTC (permalink / raw)
To: Ajeet Singh, qemu-devel; +Cc: Warner Losh, Stacey Son, Ajeet Singh, Kyle Evans
On 7/7/24 12:11, Ajeet Singh wrote:
> From: Stacey Son<sson@FreeBSD.org>
>
> function to retrieve machine context,it populates the provided
> target_mcontext_t structure with information from the CPUARMState
> registers.
>
> Signed-off-by: Stacey Son<sson@FreeBSD.org>
> Signed-off-by: Ajeet Singh<itachis@FreeBSD.org>
> Co-authored-by: Kyle Evans<kevans@FreeBSD.org>
> ---
> bsd-user/aarch64/signal.c | 30 ++++++++++++++++++++++++++++++
> 1 file changed, 30 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2 6/8] bsd-user:Add setup_sigframe_arch function for ARM AArch64
2024-07-07 19:11 [PATCH v2 0/8] ARM AArch64 Support for BSD Ajeet Singh
` (4 preceding siblings ...)
2024-07-07 19:11 ` [PATCH v2 5/8] bsd-user:Add get_mcontext function for ARM AArch64 Ajeet Singh
@ 2024-07-07 19:11 ` Ajeet Singh
2024-07-07 19:11 ` [PATCH v2 7/8] bsd-user:Add set_mcontext " Ajeet Singh
` (2 subsequent siblings)
8 siblings, 0 replies; 13+ messages in thread
From: Ajeet Singh @ 2024-07-07 19:11 UTC (permalink / raw)
To: qemu-devel; +Cc: Warner Losh, Ajeet Singh, Richard Henderson
From: Warner Losh <imp@bsdimp.com>
The function utilizes the `get_mcontext` function to retrieve the machine
context for the current CPUARMState
Signed-off-by: Warner Losh <imp@bsdimp.com>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
bsd-user/aarch64/signal.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/bsd-user/aarch64/signal.c b/bsd-user/aarch64/signal.c
index ab3bf8558a..43c886e603 100644
--- a/bsd-user/aarch64/signal.c
+++ b/bsd-user/aarch64/signal.c
@@ -81,3 +81,17 @@ abi_long get_mcontext(CPUARMState *regs, target_mcontext_t *mcp, int flags)
return err;
}
+
+/*
+ * Compare to arm64/arm64/exec_machdep.c sendsig()
+ * Assumes that the memory is locked if frame points to user memory.
+ */
+abi_long setup_sigframe_arch(CPUARMState *env, abi_ulong frame_addr,
+ struct target_sigframe *frame, int flags)
+{
+ target_mcontext_t *mcp = &frame->sf_uc.uc_mcontext;
+
+ get_mcontext(env, mcp, flags);
+ return 0;
+}
+
--
2.34.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v2 7/8] bsd-user:Add set_mcontext function for ARM AArch64
2024-07-07 19:11 [PATCH v2 0/8] ARM AArch64 Support for BSD Ajeet Singh
` (5 preceding siblings ...)
2024-07-07 19:11 ` [PATCH v2 6/8] bsd-user:Add setup_sigframe_arch " Ajeet Singh
@ 2024-07-07 19:11 ` Ajeet Singh
2024-07-08 16:10 ` Richard Henderson
2024-07-07 19:11 ` [PATCH v2 8/8] bsd-user:Add AArch64 improvements and signal handling functions Ajeet Singh
2024-07-21 21:56 ` [PATCH v2 0/8] ARM AArch64 Support for BSD Warner Losh
8 siblings, 1 reply; 13+ messages in thread
From: Ajeet Singh @ 2024-07-07 19:11 UTC (permalink / raw)
To: qemu-devel; +Cc: Warner Losh, Stacey Son, Ajeet Singh
From: Stacey Son <sson@FreeBSD.org>
The function copies register values from the provided target_mcontext_t
structure to the CPUARMState registers.
Note:FP is unfinished upstream but will be a separate commit coming soon.
Signed-off-by: Stacey Son <sson@FreeBSD.org>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
---
bsd-user/aarch64/signal.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/bsd-user/aarch64/signal.c b/bsd-user/aarch64/signal.c
index 43c886e603..13faac8ce6 100644
--- a/bsd-user/aarch64/signal.c
+++ b/bsd-user/aarch64/signal.c
@@ -95,3 +95,25 @@ abi_long setup_sigframe_arch(CPUARMState *env, abi_ulong frame_addr,
return 0;
}
+/*
+ * Compare to set_mcontext() in arm64/arm64/machdep.c
+ * Assumes that the memory is locked if frame points to user memory.
+ */
+abi_long set_mcontext(CPUARMState *regs, target_mcontext_t *mcp, int srflag)
+{
+ int err = 0, i;
+ const uint64_t *gr = mcp->mc_gpregs.gp_x;
+
+ for (i = 0; i < 30; i++) {
+ regs->xregs[i] = tswap64(gr[i]);
+ }
+
+ regs->xregs[TARGET_REG_SP] = tswap64(mcp->mc_gpregs.gp_sp);
+ regs->xregs[TARGET_REG_LR] = tswap64(mcp->mc_gpregs.gp_lr);
+ regs->pc = mcp->mc_gpregs.gp_elr;
+ pstate_write(regs, mcp->mc_gpregs.gp_spsr);
+
+ /* XXX FP? */
+
+ return err;
+}
--
2.34.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH v2 7/8] bsd-user:Add set_mcontext function for ARM AArch64
2024-07-07 19:11 ` [PATCH v2 7/8] bsd-user:Add set_mcontext " Ajeet Singh
@ 2024-07-08 16:10 ` Richard Henderson
0 siblings, 0 replies; 13+ messages in thread
From: Richard Henderson @ 2024-07-08 16:10 UTC (permalink / raw)
To: Ajeet Singh, qemu-devel; +Cc: Warner Losh, Stacey Son, Ajeet Singh
On 7/7/24 12:11, Ajeet Singh wrote:
> From: Stacey Son<sson@FreeBSD.org>
>
> The function copies register values from the provided target_mcontext_t
> structure to the CPUARMState registers.
> Note:FP is unfinished upstream but will be a separate commit coming soon.
>
> Signed-off-by: Stacey Son<sson@FreeBSD.org>
> Signed-off-by: Ajeet Singh<itachis@FreeBSD.org>
> ---
> bsd-user/aarch64/signal.c | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2 8/8] bsd-user:Add AArch64 improvements and signal handling functions
2024-07-07 19:11 [PATCH v2 0/8] ARM AArch64 Support for BSD Ajeet Singh
` (6 preceding siblings ...)
2024-07-07 19:11 ` [PATCH v2 7/8] bsd-user:Add set_mcontext " Ajeet Singh
@ 2024-07-07 19:11 ` Ajeet Singh
2024-07-08 16:12 ` Richard Henderson
2024-07-21 21:56 ` [PATCH v2 0/8] ARM AArch64 Support for BSD Warner Losh
8 siblings, 1 reply; 13+ messages in thread
From: Ajeet Singh @ 2024-07-07 19:11 UTC (permalink / raw)
To: qemu-devel; +Cc: Warner Losh, Stacey Son, Ajeet Singh
From: Stacey Son <sson@FreeBSD.org>
Added get_ucontext_sigreturn function to check processor state ensuring current execution mode is EL0 and no flags
indicating interrupts or exceptions are set.
Updated AArch64 code to use CF directly without reading/writing the entire processor state, improving efficiency.
Changed FP data structures to use Int128 instead of __uint128_t, leveraging QEMU's generic mechanism for referencing this type.
Signed-off-by: Stacey Son <sson@FreeBSD.org>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Signed-off-by: Warner Losh <imp@bsdimp.com>
---
bsd-user/aarch64/signal.c | 20 +++++++++++++++++++-
bsd-user/aarch64/target_arch_cpu.h | 7 ++-----
bsd-user/aarch64/target_arch_reg.h | 2 +-
bsd-user/aarch64/target_arch_signal.h | 2 +-
bsd-user/qemu.h | 3 +++
5 files changed, 26 insertions(+), 8 deletions(-)
diff --git a/bsd-user/aarch64/signal.c b/bsd-user/aarch64/signal.c
index 13faac8ce6..6bc73a798f 100644
--- a/bsd-user/aarch64/signal.c
+++ b/bsd-user/aarch64/signal.c
@@ -21,7 +21,7 @@
#include "qemu.h"
/*
- * Compare to sendsig() in sys/arm64/arm64/machdep.c
+ * Compare to sendsig() in sys/arm64/arm64/exec_machdep.c
* Assumes that target stack frame memory is locked.
*/
abi_long set_sigtramp_args(CPUARMState *regs, int sig,
@@ -117,3 +117,21 @@ abi_long set_mcontext(CPUARMState *regs, target_mcontext_t *mcp, int srflag)
return err;
}
+
+/* Compare to sys_sigreturn() in arm64/arm64/machdep.c */
+abi_long get_ucontext_sigreturn(CPUARMState *regs, abi_ulong target_sf,
+ abi_ulong *target_uc)
+{
+ uint32_t pstate = pstate_read(regs);
+
+ *target_uc = 0;
+
+ if ((pstate & PSTATE_M) != PSTATE_MODE_EL0t ||
+ (pstate & (PSTATE_F | PSTATE_I | PSTATE_A | PSTATE_D)) != 0) {
+ return -TARGET_EINVAL;
+ }
+
+ *target_uc = target_sf;
+
+ return 0;
+}
diff --git a/bsd-user/aarch64/target_arch_cpu.h b/bsd-user/aarch64/target_arch_cpu.h
index 4e950305d3..408aef2bb5 100644
--- a/bsd-user/aarch64/target_arch_cpu.h
+++ b/bsd-user/aarch64/target_arch_cpu.h
@@ -47,7 +47,6 @@ static inline void target_cpu_loop(CPUARMState *env)
CPUState *cs = env_cpu(env);
int trapnr, ec, fsc, si_code, si_signo;
uint64_t code, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8;
- uint32_t pstate;
abi_long ret;
for (;;) {
@@ -87,18 +86,16 @@ static inline void target_cpu_loop(CPUARMState *env)
* The carry bit is cleared for no error; set for error.
* See arm64/arm64/vm_machdep.c cpu_set_syscall_retval()
*/
- pstate = pstate_read(env);
if (ret >= 0) {
- pstate &= ~PSTATE_C;
+ env->CF = 0;
env->xregs[0] = ret;
} else if (ret == -TARGET_ERESTART) {
env->pc -= 4;
break;
} else if (ret != -TARGET_EJUSTRETURN) {
- pstate |= PSTATE_C;
+ env->CF = 1;
env->xregs[0] = -ret;
}
- pstate_write(env, pstate);
break;
case EXCP_INTERRUPT:
diff --git a/bsd-user/aarch64/target_arch_reg.h b/bsd-user/aarch64/target_arch_reg.h
index 5c7154f0c1..b53302e7f7 100644
--- a/bsd-user/aarch64/target_arch_reg.h
+++ b/bsd-user/aarch64/target_arch_reg.h
@@ -31,7 +31,7 @@ typedef struct target_reg {
} target_reg_t;
typedef struct target_fpreg {
- __uint128_t fp_q[32];
+ Int128 fp_q[32];
uint32_t fp_sr;
uint32_t fp_cr;
} target_fpreg_t;
diff --git a/bsd-user/aarch64/target_arch_signal.h b/bsd-user/aarch64/target_arch_signal.h
index df17173316..bff752a67a 100644
--- a/bsd-user/aarch64/target_arch_signal.h
+++ b/bsd-user/aarch64/target_arch_signal.h
@@ -49,7 +49,7 @@ struct target_gpregs {
};
struct target_fpregs {
- __uint128_t fp_q[32];
+ Int128 fp_q[32];
uint32_t fp_sr;
uint32_t fp_cr;
uint32_t fp_flags;
diff --git a/bsd-user/qemu.h b/bsd-user/qemu.h
index 9d2fc7148e..3736c41786 100644
--- a/bsd-user/qemu.h
+++ b/bsd-user/qemu.h
@@ -17,6 +17,9 @@
#ifndef QEMU_H
#define QEMU_H
+#include <sys/param.h>
+
+#include "qemu/int128.h"
#include "cpu.h"
#include "qemu/units.h"
#include "exec/cpu_ldst.h"
--
2.34.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH v2 8/8] bsd-user:Add AArch64 improvements and signal handling functions
2024-07-07 19:11 ` [PATCH v2 8/8] bsd-user:Add AArch64 improvements and signal handling functions Ajeet Singh
@ 2024-07-08 16:12 ` Richard Henderson
0 siblings, 0 replies; 13+ messages in thread
From: Richard Henderson @ 2024-07-08 16:12 UTC (permalink / raw)
To: Ajeet Singh, qemu-devel; +Cc: Warner Losh, Stacey Son, Ajeet Singh
On 7/7/24 12:11, Ajeet Singh wrote:
> From: Stacey Son<sson@FreeBSD.org>
>
> Added get_ucontext_sigreturn function to check processor state ensuring current execution mode is EL0 and no flags
> indicating interrupts or exceptions are set.
> Updated AArch64 code to use CF directly without reading/writing the entire processor state, improving efficiency.
> Changed FP data structures to use Int128 instead of __uint128_t, leveraging QEMU's generic mechanism for referencing this type.
>
> Signed-off-by: Stacey Son<sson@FreeBSD.org>
> Signed-off-by: Ajeet Singh<itachis@FreeBSD.org>
> Signed-off-by: Warner Losh<imp@bsdimp.com>
> ---
> bsd-user/aarch64/signal.c | 20 +++++++++++++++++++-
> bsd-user/aarch64/target_arch_cpu.h | 7 ++-----
> bsd-user/aarch64/target_arch_reg.h | 2 +-
> bsd-user/aarch64/target_arch_signal.h | 2 +-
> bsd-user/qemu.h | 3 +++
> 5 files changed, 26 insertions(+), 8 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 0/8] ARM AArch64 Support for BSD
2024-07-07 19:11 [PATCH v2 0/8] ARM AArch64 Support for BSD Ajeet Singh
` (7 preceding siblings ...)
2024-07-07 19:11 ` [PATCH v2 8/8] bsd-user:Add AArch64 improvements and signal handling functions Ajeet Singh
@ 2024-07-21 21:56 ` Warner Losh
8 siblings, 0 replies; 13+ messages in thread
From: Warner Losh @ 2024-07-21 21:56 UTC (permalink / raw)
To: Ajeet Singh; +Cc: qemu-devel, Ajeet Singh
[-- Attachment #1: Type: text/plain, Size: 3641 bytes --]
Queued for my 9.1 pull request...
Thanks! Sorry for the delay...
Warner
On Sun, Jul 7, 2024 at 1:11 PM Ajeet Singh <itachis6234@gmail.com> wrote:
> Patch 1: Previous patches 1 to 5, which were reviewed and acked, have been
> folded into this patch.Some changes that were suggested,
> such as replacing "pstate &= ~PSTATE_C" with faster constructs
> like "env->CF = 0", have been addressed in patch 8.
> Patch 2: In this patch, patches 6 to 11 have been folded. Changes such as
> using "ROUND_DOWN" for stack pointer calculation
> and replacing "__uint128_t" with "Int128" in the following patch
> 8 have been addressed. Also, "CPUARMState" will be
> changed to "CPUArchState" in the upcoming version, and the issue
> with "-R" is being worked on separately.
> Patch 3: Patches 12 to 16 were reviewed and folded. The function
> "get_second_rval" will be used upstream.
> Patch 4: Patches 17 to 19 were folded, and "__uint128_t" to "Int128" has
> been fixed in patch 8. Also, the suggestion to
> use "const_le32()" has been deferred for now.
> Patch 5: Previously patch 20, the FP suggestion is being deferred, but the
> patch is ready for review.
> Patch 6: Previously patch 21 has been reviewed.
> Patch 7: Previously patch 22, same as patch 5.
> Patch 8: Previously patch 23. For now, no changes, but issues of other
> patches have been addressed, such as updating
> AArch64 code to use CF directly and changing FP data structures
> to use Int128 instead of __uint128_t.
>
> Stacey Son (6):
> bsd-user:Add CPU initialization and management functions
> bsd-user:Add AArch64 register handling and related functions
> bsd-user:Add ARM AArch64 signal handling support
> bsd-user:Add get_mcontext function for ARM AArch64
> bsd-user:Add set_mcontext function for ARM AArch64
> bsd-user:Add AArch64 improvements and signal handling functions
>
> Warner Losh (2):
> bsd-user:Add ARM AArch64 support and capabilities
> bsd-user:Add setup_sigframe_arch function for ARM AArch64
>
> bsd-user/aarch64/signal.c | 137 +++++++++++++++++
> bsd-user/aarch64/target_arch.h | 28 ++++
> bsd-user/aarch64/target_arch_cpu.c | 31 ++++
> bsd-user/aarch64/target_arch_cpu.h | 188 ++++++++++++++++++++++++
> bsd-user/aarch64/target_arch_elf.h | 165 +++++++++++++++++++++
> bsd-user/aarch64/target_arch_reg.h | 56 +++++++
> bsd-user/aarch64/target_arch_signal.h | 80 ++++++++++
> bsd-user/aarch64/target_arch_sigtramp.h | 48 ++++++
> bsd-user/aarch64/target_arch_sysarch.h | 42 ++++++
> bsd-user/aarch64/target_arch_thread.h | 61 ++++++++
> bsd-user/aarch64/target_arch_vmparam.h | 74 ++++++++++
> bsd-user/aarch64/target_syscall.h | 51 +++++++
> bsd-user/qemu.h | 3 +
> 13 files changed, 964 insertions(+)
> create mode 100644 bsd-user/aarch64/signal.c
> create mode 100644 bsd-user/aarch64/target_arch.h
> create mode 100644 bsd-user/aarch64/target_arch_cpu.c
> create mode 100644 bsd-user/aarch64/target_arch_cpu.h
> create mode 100644 bsd-user/aarch64/target_arch_elf.h
> create mode 100644 bsd-user/aarch64/target_arch_reg.h
> create mode 100644 bsd-user/aarch64/target_arch_signal.h
> create mode 100644 bsd-user/aarch64/target_arch_sigtramp.h
> create mode 100644 bsd-user/aarch64/target_arch_sysarch.h
> create mode 100644 bsd-user/aarch64/target_arch_thread.h
> create mode 100644 bsd-user/aarch64/target_arch_vmparam.h
> create mode 100644 bsd-user/aarch64/target_syscall.h
>
> --
> 2.34.1
>
>
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^ permalink raw reply [flat|nested] 13+ messages in thread