Re: [PATCH v4 2/3] hw/arm: Connect STM32L4x5 GPIO to STM32L4x5 SoC

["Philippe Mathieu-Daudé" <philmd@linaro.org>]

On 7/2/24 14:23, Inès Varhol wrote:
> Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
> ---
>   include/hw/arm/stm32l4x5_soc.h |  2 +
>   hw/arm/stm32l4x5_soc.c         | 78 ++++++++++++++++++++++++++++------
>   hw/arm/Kconfig                 |  3 +-
>   3 files changed, 68 insertions(+), 15 deletions(-)


> diff --git a/hw/arm/stm32l4x5_soc.c b/hw/arm/stm32l4x5_soc.c
> index 347a5377e5..ff38585dd6 100644
> --- a/hw/arm/stm32l4x5_soc.c
> +++ b/hw/arm/stm32l4x5_soc.c
> @@ -78,6 +78,32 @@ static const int exti_irq[NUM_EXTI_IRQ] = {
>   #define RCC_BASE_ADDRESS 0x40021000
>   #define RCC_IRQ 5
>   
> +static const uint32_t gpio_addr[

NUM_GPIOS

> ] = {
> +    0x48000000,
> +    0x48000400,
> +    0x48000800,
> +    0x48000C00,
> +    0x48001000,
> +    0x48001400,
> +    0x48001800,
> +    0x48001C00,
> +};
> +
> +static const struct {

gpio_addr[] should be moved in this same struct (eventually
naming it stm32l4x5_gpio_cfg), since the init val are related
to the gpio peripheral / base addr.

> +    uint32_t moder;
> +    uint32_t ospeedr;
> +    uint32_t pupdr;
> +} stm32l4x5_gpio_initval[NUM_GPIOS] = {
> +    { 0xABFFFFFF, 0x0C000000, 0x64000000 },
> +    { 0xFFFFFEBF, 0x00000000, 0x00000100 },
> +    { 0xFFFFFFFF, 0x00000000, 0x00000000 },
> +    { 0xFFFFFFFF, 0x00000000, 0x00000000 },
> +    { 0xFFFFFFFF, 0x00000000, 0x00000000 },
> +    { 0xFFFFFFFF, 0x00000000, 0x00000000 },
> +    { 0xFFFFFFFF, 0x00000000, 0x00000000 },
> +    { 0x0000000F, 0x00000000, 0x00000000 },
> +};

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>