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[176.184.18.96]) by smtp.gmail.com with ESMTPSA id v11-20020a5d4b0b000000b0033d90b314e7sm2631441wrq.101.2024.02.23.04.25.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 23 Feb 2024 04:25:14 -0800 (PST) Message-ID: Date: Fri, 23 Feb 2024 13:25:12 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 2/3] hw/arm: Connect STM32L4x5 GPIO to STM32L4x5 SoC Content-Language: en-US To: =?UTF-8?Q?In=C3=A8s_Varhol?= , qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Laurent Vivier , Paolo Bonzini , Peter Maydell , Alistair Francis , Samuel Tardieu , Thomas Huth , Arnaud Minier References: <20240207132517.198348-1-ines.varhol@telecom-paris.fr> <20240207132517.198348-3-ines.varhol@telecom-paris.fr> From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20240207132517.198348-3-ines.varhol@telecom-paris.fr> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 7/2/24 14:23, Inès Varhol wrote: > Signed-off-by: Arnaud Minier > Signed-off-by: Inès Varhol > --- > include/hw/arm/stm32l4x5_soc.h | 2 + > hw/arm/stm32l4x5_soc.c | 78 ++++++++++++++++++++++++++++------ > hw/arm/Kconfig | 3 +- > 3 files changed, 68 insertions(+), 15 deletions(-) > diff --git a/hw/arm/stm32l4x5_soc.c b/hw/arm/stm32l4x5_soc.c > index 347a5377e5..ff38585dd6 100644 > --- a/hw/arm/stm32l4x5_soc.c > +++ b/hw/arm/stm32l4x5_soc.c > @@ -78,6 +78,32 @@ static const int exti_irq[NUM_EXTI_IRQ] = { > #define RCC_BASE_ADDRESS 0x40021000 > #define RCC_IRQ 5 > > +static const uint32_t gpio_addr[ NUM_GPIOS > ] = { > + 0x48000000, > + 0x48000400, > + 0x48000800, > + 0x48000C00, > + 0x48001000, > + 0x48001400, > + 0x48001800, > + 0x48001C00, > +}; > + > +static const struct { gpio_addr[] should be moved in this same struct (eventually naming it stm32l4x5_gpio_cfg), since the init val are related to the gpio peripheral / base addr. > + uint32_t moder; > + uint32_t ospeedr; > + uint32_t pupdr; > +} stm32l4x5_gpio_initval[NUM_GPIOS] = { > + { 0xABFFFFFF, 0x0C000000, 0x64000000 }, > + { 0xFFFFFEBF, 0x00000000, 0x00000100 }, > + { 0xFFFFFFFF, 0x00000000, 0x00000000 }, > + { 0xFFFFFFFF, 0x00000000, 0x00000000 }, > + { 0xFFFFFFFF, 0x00000000, 0x00000000 }, > + { 0xFFFFFFFF, 0x00000000, 0x00000000 }, > + { 0xFFFFFFFF, 0x00000000, 0x00000000 }, > + { 0x0000000F, 0x00000000, 0x00000000 }, > +}; Reviewed-by: Philippe Mathieu-Daudé