qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Richard Henderson <richard.henderson@linaro.org>
To: Weiwei Li <liweiwei@iscas.ac.cn>,
	palmer@dabbelt.com, alistair.francis@wdc.com,
	bin.meng@windriver.com, qemu-riscv@nongnu.org,
	qemu-devel@nongnu.org
Cc: wangjunqiang@iscas.ac.cn, lazyparser@gmail.com
Subject: Re: [PATCH v4 7/9] target/riscv: add support for Zcmt extension
Date: Fri, 18 Nov 2022 02:24:47 -0800	[thread overview]
Message-ID: <f3525752-ac4b-f355-7ed5-3e9cf88e3116@linaro.org> (raw)
In-Reply-To: <20221118071704.26959-8-liweiwei@iscas.ac.cn>

On 11/17/22 23:17, Weiwei Li wrote:
> +target_ulong HELPER(cm_jalt)(CPURISCVState *env, target_ulong index,
> +                             target_ulong next_pc)
> +{
> +
> +#if !defined(CONFIG_USER_ONLY)
> +    RISCVException ret = smstateen_acc_ok(env, 0, SMSTATEEN0_JVT);
> +    if (ret != RISCV_EXCP_NONE) {
> +        riscv_raise_exception(env, ret, GETPC());
> +    }
> +#endif
> +
> +    target_ulong target = next_pc;
> +    target_ulong val = 0;
> +    int xlen = riscv_cpu_xlen(env);
> +
> +    val = env->jvt;
> +
> +    uint8_t mode = get_field(val, JVT_MODE);
> +    target_ulong base = get_field(val, JVT_BASE);
> +    target_ulong t0;
> +
> +    if (mode != 0) {
> +        riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> +    }
> +
> +    if (xlen == 32) {
> +        t0 = base + (index << 2);
> +        target = cpu_ldl_code(env, t0);
> +    } else {
> +        t0 = base + (index << 3);
> +        target = cpu_ldq_code(env, t0);
> +    }

Much better.  The only problem is here where cpu_ld*_code does not have support for unwind 
from exception.  If this load faults, we won't update env->pc on the way out (we are 
normally loading for code during translation, where pc is perforce up to date).  I should 
have noticed this before.

The way to fix this is to update cpu_pc to the current instruction before calling the 
helper.  At which point none of the other exception exits need to unwind either, so you 
can replace all of the GETPC() with 0.

> +
> +    /* index >= 32 for cm.jalt, otherwise for cm.jt */
> +    if (index >= 32) {
> +        env->gpr[1] = next_pc;
> +    }

This is simple enough to do in the caller, and then you don't need to pass in next_pc.
And since you don't modify xRA in the helper you can do

DEF_HELPER_FLAGS_3(cm_jt, TCG_CALL_NO_WG, tl, env, tl, tl)

static bool trans_cm_jalt(DisasContext *ctx, arg_cm_jalt *a)
{
     REQUIRE_ZCMT(ctx);

     /*
      * Update pc to current for the non-unwinding exception
      * that might come from cpu_ld*_code() in the helper.
      */
     tcg_gen_movi_tl(cpu_pc, s->base.pc_next);
     gen_helper_cm_jt(cpu_pc, cpu_env, tcg_constant_i32(a->index))

     /* c.jt vs c.jalt depends on the index. */
     if (a->index >= 32) {
         gen_set_gpri(ctx, xRA, ctx->pc_succ_insn);
     }
     tcg_gen_lookup_and_goto_ptr();
     ctx->base.is_jmp = DISAS_NORETURN;
     return true;
}


r~


  reply	other threads:[~2022-11-18 10:25 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-18  7:16 [PATCH v4 0/9] support subsets of code size reduction extension Weiwei Li
2022-11-18  7:16 ` [PATCH v4 1/9] target/riscv: add cfg properties for Zc* extension Weiwei Li
2022-11-18  7:16 ` [PATCH v4 2/9] target/riscv: add support for Zca extension Weiwei Li
2022-11-18  7:16 ` [PATCH v4 3/9] target/riscv: add support for Zcf extension Weiwei Li
2022-11-18  7:16 ` [PATCH v4 4/9] target/riscv: add support for Zcd extension Weiwei Li
2022-11-18  7:17 ` [PATCH v4 5/9] target/riscv: add support for Zcb extension Weiwei Li
2022-11-18  7:17 ` [PATCH v4 6/9] target/riscv: add support for Zcmp extension Weiwei Li
2022-11-18 10:02   ` Richard Henderson
2022-11-18  7:17 ` [PATCH v4 7/9] target/riscv: add support for Zcmt extension Weiwei Li
2022-11-18 10:24   ` Richard Henderson [this message]
2022-11-18 11:59     ` weiwei
2022-11-18  7:17 ` [PATCH v4 8/9] target/riscv: expose properties for Zc* extension Weiwei Li
2022-11-18  7:17 ` [PATCH v4 9/9] disas/riscv.c: add disasm support for Zc* Weiwei Li

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=f3525752-ac4b-f355-7ed5-3e9cf88e3116@linaro.org \
    --to=richard.henderson@linaro.org \
    --cc=alistair.francis@wdc.com \
    --cc=bin.meng@windriver.com \
    --cc=lazyparser@gmail.com \
    --cc=liweiwei@iscas.ac.cn \
    --cc=palmer@dabbelt.com \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-riscv@nongnu.org \
    --cc=wangjunqiang@iscas.ac.cn \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).