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([2602:47:d48a:1201:90b2:345f:bf0a:c412]) by smtp.gmail.com with ESMTPSA id e89-20020a17090a6fe200b002137d3da760sm5060350pjk.39.2022.11.18.02.24.48 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 18 Nov 2022 02:24:49 -0800 (PST) Message-ID: Date: Fri, 18 Nov 2022 02:24:47 -0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 Subject: Re: [PATCH v4 7/9] target/riscv: add support for Zcmt extension Content-Language: en-US To: Weiwei Li , palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: wangjunqiang@iscas.ac.cn, lazyparser@gmail.com References: <20221118071704.26959-1-liweiwei@iscas.ac.cn> <20221118071704.26959-8-liweiwei@iscas.ac.cn> From: Richard Henderson In-Reply-To: <20221118071704.26959-8-liweiwei@iscas.ac.cn> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 11/17/22 23:17, Weiwei Li wrote: > +target_ulong HELPER(cm_jalt)(CPURISCVState *env, target_ulong index, > + target_ulong next_pc) > +{ > + > +#if !defined(CONFIG_USER_ONLY) > + RISCVException ret = smstateen_acc_ok(env, 0, SMSTATEEN0_JVT); > + if (ret != RISCV_EXCP_NONE) { > + riscv_raise_exception(env, ret, GETPC()); > + } > +#endif > + > + target_ulong target = next_pc; > + target_ulong val = 0; > + int xlen = riscv_cpu_xlen(env); > + > + val = env->jvt; > + > + uint8_t mode = get_field(val, JVT_MODE); > + target_ulong base = get_field(val, JVT_BASE); > + target_ulong t0; > + > + if (mode != 0) { > + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); > + } > + > + if (xlen == 32) { > + t0 = base + (index << 2); > + target = cpu_ldl_code(env, t0); > + } else { > + t0 = base + (index << 3); > + target = cpu_ldq_code(env, t0); > + } Much better. The only problem is here where cpu_ld*_code does not have support for unwind from exception. If this load faults, we won't update env->pc on the way out (we are normally loading for code during translation, where pc is perforce up to date). I should have noticed this before. The way to fix this is to update cpu_pc to the current instruction before calling the helper. At which point none of the other exception exits need to unwind either, so you can replace all of the GETPC() with 0. > + > + /* index >= 32 for cm.jalt, otherwise for cm.jt */ > + if (index >= 32) { > + env->gpr[1] = next_pc; > + } This is simple enough to do in the caller, and then you don't need to pass in next_pc. And since you don't modify xRA in the helper you can do DEF_HELPER_FLAGS_3(cm_jt, TCG_CALL_NO_WG, tl, env, tl, tl) static bool trans_cm_jalt(DisasContext *ctx, arg_cm_jalt *a) { REQUIRE_ZCMT(ctx); /* * Update pc to current for the non-unwinding exception * that might come from cpu_ld*_code() in the helper. */ tcg_gen_movi_tl(cpu_pc, s->base.pc_next); gen_helper_cm_jt(cpu_pc, cpu_env, tcg_constant_i32(a->index)) /* c.jt vs c.jalt depends on the index. */ if (a->index >= 32) { gen_set_gpri(ctx, xRA, ctx->pc_succ_insn); } tcg_gen_lookup_and_goto_ptr(); ctx->base.is_jmp = DISAS_NORETURN; return true; } r~