Re: [PATCH v3 1/2] target/riscv: Add BOSC's Xiangshan Kunminghu CPU

[Ran Wang <wangran@bosc.ac.cn>]

Hi Alistair

On 2025/4/24 18:49, Alistair Francis wrote:
> On Tue, Apr 8, 2025 at 12:23 PM Huang Borong <huangborong@bosc.ac.cn> wrote:
>>
>> Add a CPU entry for the Xiangshan Kunminghu CPU, an open-source,
>> high-performance RISC-V processor. More details can be found at:

<snip>

>> +    cpu->cfg.ext_ssaia = true;
>> +
>> +    /* RVA23 Profiles */
>> +    cpu->cfg.ext_zicbom = true;
>> +    cpu->cfg.ext_zicbop = true;
>> +    cpu->cfg.ext_zicboz = true;
>> +    cpu->cfg.ext_svade = true;
>> +
>> +#ifndef CONFIG_USER_ONLY
>> +    set_satp_mode_max_supported(cpu, VM_1_10_SV48);
>> +#endif
>> +}
>> +
> 
> Sorry about this, but we just merged a new way of defining CPU types.
> Can you please rebase on
> https://github.com/alistair23/qemu/tree/riscv-to-apply.next to use the
> new macros? It shouldn't be much work, just a little restructuring.
> 
> When sending a new version can you also include a cover letter [1]
> 
> 1: https://www.qemu.org/docs/master/devel/submitting-a-patch.html#include-a-meaningful-cover-letter

Sure, Borong just left BOSC and I will take over his job and send out 
next version patch mail later.

Thanks & Regards,

Ran

> Alistair
> 
>>   #ifdef CONFIG_TCG
>>   static void rv128_base_cpu_init(Object *obj)
>>   {
>> @@ -3261,6 +3331,8 @@ static const TypeInfo riscv_cpu_type_infos[] = {
>>       DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1,  MXL_RV64,  rv64_veyron_v1_cpu_init),
>>       DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU,
>>                                                    MXL_RV64, rv64_xiangshan_nanhu_cpu_init),
>> +    DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_XIANGSHAN_KMH,
>> +                                                 MXL_RV64,  rv64_xiangshan_kmh_cpu_init),
>>   #ifdef CONFIG_TCG
>>       DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128,   MXL_RV128, rv128_base_cpu_init),
>>   #endif /* CONFIG_TCG */
>> --
>> 2.34.1
>>
>>