From: Daniel Henrique Barboza <danielhb413@gmail.com>
To: "Cédric Le Goater" <clg@kaod.org>,
qemu-ppc@nongnu.org, qemu-devel@nongnu.org
Cc: Alexey Kardashevskiy <aik@ozlabs.ru>,
Frederic Barrat <fbarrat@linux.ibm.com>,
Greg Kurz <groug@kaod.org>,
David Gibson <david@gibson.dropbear.id.au>
Subject: Re: [PATCH v3 13/18] pnv/xive2: Introduce new capability bits
Date: Fri, 25 Feb 2022 13:13:31 -0300 [thread overview]
Message-ID: <f3b49249-1018-53f6-7e91-e922989fa87d@gmail.com> (raw)
In-Reply-To: <20211126115349.2737605-14-clg@kaod.org>
On 11/26/21 08:53, Cédric Le Goater wrote:
> These bits control the availability of interrupt features : StoreEOI,
> PHB PQ_disable, PHB Address-Based Trigger and the overall XIVE
> exploitation mode. These bits can be set at early boot time of the
> system to activate/deactivate a feature for testing purposes. The
> default value should be '1'.
>
> The 'XIVE exploitation mode' bit is a software bit that skiboot could
> use to disable the XIVE OS interface and propose a P8 style XICS
> interface instead. There are no plans for that for the moment.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> hw/intc/pnv_xive2_regs.h | 5 +++++
> hw/intc/pnv_xive2.c | 4 ++--
> 2 files changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/hw/intc/pnv_xive2_regs.h b/hw/intc/pnv_xive2_regs.h
> index 084fccc8d3e9..46d4fb378135 100644
> --- a/hw/intc/pnv_xive2_regs.h
> +++ b/hw/intc/pnv_xive2_regs.h
> @@ -31,6 +31,11 @@
> #define CQ_XIVE_CAP_VP_INT_PRIO_8 3
> #define CQ_XIVE_CAP_BLOCK_ID_WIDTH PPC_BITMASK(12, 13)
>
> +#define CQ_XIVE_CAP_PHB_PQ_DISABLE PPC_BIT(56)
> +#define CQ_XIVE_CAP_PHB_ABT PPC_BIT(57)
> +#define CQ_XIVE_CAP_EXPLOITATION_MODE PPC_BIT(58)
> +#define CQ_XIVE_CAP_STORE_EOI PPC_BIT(59)
> +
> /* XIVE2 Configuration */
> #define X_CQ_XIVE_CFG 0x03
> #define CQ_XIVE_CFG 0x018
> diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c
> index 186ab66e105d..cb12cea14fc6 100644
> --- a/hw/intc/pnv_xive2.c
> +++ b/hw/intc/pnv_xive2.c
> @@ -1708,9 +1708,9 @@ static const MemoryRegionOps pnv_xive2_nvpg_ops = {
> };
>
> /*
> - * POWER10 default capabilities: 0x2000120076f00000
> + * POWER10 default capabilities: 0x2000120076f000FC
> */
> -#define PNV_XIVE2_CAPABILITIES 0x2000120076f00000
> +#define PNV_XIVE2_CAPABILITIES 0x2000120076f000FC
>
> /*
> * POWER10 default configuration: 0x0030000033000000
next prev parent reply other threads:[~2022-02-25 16:26 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-26 11:53 [PATCH v3 00/18] ppc/pnv: Extend the powernv10 machine Cédric Le Goater
2021-11-26 11:53 ` [PATCH v3 01/18] ppc/xive2: Introduce a XIVE2 core framework Cédric Le Goater
2022-02-25 13:44 ` Daniel Henrique Barboza
2021-11-26 11:53 ` [PATCH v3 02/18] ppc/xive2: Introduce a presenter matching routine Cédric Le Goater
2022-02-25 13:44 ` Daniel Henrique Barboza
2021-11-26 11:53 ` [PATCH v3 03/18] ppc/pnv: Add a XIVE2 controller to the POWER10 chip Cédric Le Goater
2022-02-25 14:01 ` Daniel Henrique Barboza
2021-11-26 11:53 ` [PATCH v3 04/18] ppc/pnv: Add a OCC model for POWER10 Cédric Le Goater
2021-11-26 11:53 ` [PATCH v3 05/18] ppc/pnv: Add POWER10 quads Cédric Le Goater
2021-11-26 11:53 ` [PATCH v3 06/18] ppc/pnv: Add model for POWER10 PHB5 PCIe Host bridge Cédric Le Goater
2022-02-25 14:09 ` Daniel Henrique Barboza
2021-11-26 11:53 ` [PATCH v3 07/18] ppc/pnv: Add a HOMER model to POWER10 Cédric Le Goater
2021-11-26 11:53 ` [PATCH v3 08/18] ppc/psi: Add support for StoreEOI and 64k ESB pages (POWER10) Cédric Le Goater
2022-02-25 14:11 ` Daniel Henrique Barboza
2021-11-26 11:53 ` [PATCH v3 09/18] ppc/xive2: Add support for notification injection on ESB pages Cédric Le Goater
2022-02-25 14:18 ` Daniel Henrique Barboza
2021-11-26 11:53 ` [PATCH v3 10/18] ppc/xive: Add support for PQ state bits offload Cédric Le Goater
2022-02-25 16:00 ` Daniel Henrique Barboza
2021-11-26 11:53 ` [PATCH v3 11/18] ppc/pnv: Add support for PQ offload on PHB5 Cédric Le Goater
2022-02-25 16:06 ` Daniel Henrique Barboza
2021-11-26 11:53 ` [PATCH v3 12/18] ppc/pnv: Add support for PHB5 "Address-based trigger" mode Cédric Le Goater
2022-02-25 16:11 ` Daniel Henrique Barboza
2021-11-26 11:53 ` [PATCH v3 13/18] pnv/xive2: Introduce new capability bits Cédric Le Goater
2022-02-25 16:13 ` Daniel Henrique Barboza [this message]
2021-11-26 11:53 ` [PATCH v3 14/18] ppc/pnv: add XIVE Gen2 TIMA support Cédric Le Goater
2022-02-25 16:26 ` Daniel Henrique Barboza
2021-11-26 11:53 ` [PATCH v3 15/18] pnv/xive2: Add support XIVE2 P9-compat mode (or Gen1) Cédric Le Goater
2022-02-25 16:28 ` Daniel Henrique Barboza
2021-11-26 11:53 ` [PATCH v3 16/18] xive2: Add a get_config() handler for the router configuration Cédric Le Goater
2022-02-25 16:29 ` Daniel Henrique Barboza
2021-11-26 11:53 ` [PATCH v3 17/18] pnv/xive2: Add support for automatic save&restore Cédric Le Goater
2022-02-25 16:33 ` Daniel Henrique Barboza
2021-11-26 11:53 ` [PATCH v3 18/18] pnv/xive2: Add support for 8bits thread id Cédric Le Goater
2022-02-25 16:33 ` Daniel Henrique Barboza
2022-01-11 13:34 ` [PATCH v3 00/18] ppc/pnv: Extend the powernv10 machine Daniel Henrique Barboza
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=f3b49249-1018-53f6-7e91-e922989fa87d@gmail.com \
--to=danielhb413@gmail.com \
--cc=aik@ozlabs.ru \
--cc=clg@kaod.org \
--cc=david@gibson.dropbear.id.au \
--cc=fbarrat@linux.ibm.com \
--cc=groug@kaod.org \
--cc=qemu-devel@nongnu.org \
--cc=qemu-ppc@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).