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([2804:431:c7c6:bec1:d9bb:8ce0:5ce7:a377]) by smtp.gmail.com with ESMTPSA id q14-20020a4a330e000000b002e89ed90006sm1265189ooq.44.2022.02.25.08.13.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 25 Feb 2022 08:13:35 -0800 (PST) Message-ID: Date: Fri, 25 Feb 2022 13:13:31 -0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [PATCH v3 13/18] pnv/xive2: Introduce new capability bits Content-Language: en-US To: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= , qemu-ppc@nongnu.org, qemu-devel@nongnu.org References: <20211126115349.2737605-1-clg@kaod.org> <20211126115349.2737605-14-clg@kaod.org> From: Daniel Henrique Barboza In-Reply-To: <20211126115349.2737605-14-clg@kaod.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::334 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::334; envelope-from=danielhb413@gmail.com; helo=mail-ot1-x334.google.com X-Spam_score_int: -3 X-Spam_score: -0.4 X-Spam_bar: / X-Spam_report: (-0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, NICE_REPLY_A=-0.001, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexey Kardashevskiy , Frederic Barrat , Greg Kurz , David Gibson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 11/26/21 08:53, Cédric Le Goater wrote: > These bits control the availability of interrupt features : StoreEOI, > PHB PQ_disable, PHB Address-Based Trigger and the overall XIVE > exploitation mode. These bits can be set at early boot time of the > system to activate/deactivate a feature for testing purposes. The > default value should be '1'. > > The 'XIVE exploitation mode' bit is a software bit that skiboot could > use to disable the XIVE OS interface and propose a P8 style XICS > interface instead. There are no plans for that for the moment. > > Signed-off-by: Cédric Le Goater > --- Reviewed-by: Daniel Henrique Barboza > hw/intc/pnv_xive2_regs.h | 5 +++++ > hw/intc/pnv_xive2.c | 4 ++-- > 2 files changed, 7 insertions(+), 2 deletions(-) > > diff --git a/hw/intc/pnv_xive2_regs.h b/hw/intc/pnv_xive2_regs.h > index 084fccc8d3e9..46d4fb378135 100644 > --- a/hw/intc/pnv_xive2_regs.h > +++ b/hw/intc/pnv_xive2_regs.h > @@ -31,6 +31,11 @@ > #define CQ_XIVE_CAP_VP_INT_PRIO_8 3 > #define CQ_XIVE_CAP_BLOCK_ID_WIDTH PPC_BITMASK(12, 13) > > +#define CQ_XIVE_CAP_PHB_PQ_DISABLE PPC_BIT(56) > +#define CQ_XIVE_CAP_PHB_ABT PPC_BIT(57) > +#define CQ_XIVE_CAP_EXPLOITATION_MODE PPC_BIT(58) > +#define CQ_XIVE_CAP_STORE_EOI PPC_BIT(59) > + > /* XIVE2 Configuration */ > #define X_CQ_XIVE_CFG 0x03 > #define CQ_XIVE_CFG 0x018 > diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c > index 186ab66e105d..cb12cea14fc6 100644 > --- a/hw/intc/pnv_xive2.c > +++ b/hw/intc/pnv_xive2.c > @@ -1708,9 +1708,9 @@ static const MemoryRegionOps pnv_xive2_nvpg_ops = { > }; > > /* > - * POWER10 default capabilities: 0x2000120076f00000 > + * POWER10 default capabilities: 0x2000120076f000FC > */ > -#define PNV_XIVE2_CAPABILITIES 0x2000120076f00000 > +#define PNV_XIVE2_CAPABILITIES 0x2000120076f000FC > > /* > * POWER10 default configuration: 0x0030000033000000