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([2602:ae:1544:6601:cb42:9f2a:fcd4:54fc]) by smtp.gmail.com with ESMTPSA id jd1-20020a170903260100b0019b0afc24e8sm14481233plb.250.2023.03.24.10.56.53 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 24 Mar 2023 10:56:54 -0700 (PDT) Message-ID: Date: Fri, 24 Mar 2023 10:56:52 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 Subject: Re: [PATCH v5 1/2] target/riscv: separate priv from mmu_idx Content-Language: en-US To: Fei Wu , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, zhiwei_liu@linux.alibaba.com, liweiwei@iscas.ac.cn Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Daniel Henrique Barboza , Christoph Muellner References: <20230324054154.414846-1-fei2.wu@intel.com> <20230324054154.414846-2-fei2.wu@intel.com> From: Richard Henderson In-Reply-To: <20230324054154.414846-2-fei2.wu@intel.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 3/23/23 22:41, Fei Wu wrote: > @@ -762,7 +764,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, > * (riscv_cpu_do_interrupt) is correct */ > MemTxResult res; > MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; > - int mode = mmu_idx & TB_FLAGS_PRIV_MMU_MASK; > + int mode = env->priv; This is not ok. Or rather, it's ok as an intermediate step before fixing the other mis-uses of the interface in get_physical_address. The interface to be provided by TCGCPUOps.tlb_fill is that (modulo tlb flushes) mmu_idx details the state we want the access to have. We describe that state with the comment you move in patch 2: +/* + * The current MMU Modes are: + * - U 0b000 + * - S 0b001 + * - S+SUM 0b010 + * - M 0b011 + * - HLV/HLVX/HSV adds 0b100 + */ Anything that's in those bits shouldn't be re-examined from env. So, in the short-term I'll give you Reviewed-by: Richard Henderson But for the long-term, let's see if we can untangle the ugly mess. I'll collect my thoughts and post some patches for discussion -- I think that will be clearer than the prose I began to write here. r~