From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com
Subject: [PATCH v2 08/27] target/riscv: Dump Hypervisor registers if enabled
Date: Fri, 25 Oct 2019 16:23:35 -0700 [thread overview]
Message-ID: <f401f134526dd811801e808f6d0bfedf2d42d5eb.1572045716.git.alistair.francis@wdc.com> (raw)
In-Reply-To: <cover.1572045716.git.alistair.francis@wdc.com>
Dump the Hypervisor registers and the current Hypervisor state.
While we are editing this code let's also dump stvec and scause.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
---
target/riscv/cpu.c | 34 ++++++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index e521ebe2e1..e66fd300fd 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -220,17 +220,51 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
CPURISCVState *env = &cpu->env;
int i;
+#if !defined(CONFIG_USER_ONLY)
+ if (riscv_has_ext(env, RVH)) {
+ qemu_fprintf(f, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env));
+ }
+#endif
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc);
#ifndef CONFIG_USER_ONLY
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus);
+ if (riscv_has_ext(env, RVH)) {
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "bstatus ", env->vsstatus);
+ }
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip ", env->mip);
+ if (riscv_has_ext(env, RVH)) {
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsip ",
+ (target_ulong)atomic_read(&env->vsip));
+ }
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", env->mie);
+ if (riscv_has_ext(env, RVH)) {
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsie ", env->vsie);
+ }
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg);
+ if (riscv_has_ext(env, RVH)) {
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hideleg ", env->hideleg);
+ }
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg);
+ if (riscv_has_ext(env, RVH)) {
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hedeleg ", env->hedeleg);
+ }
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtvec ", env->mtvec);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stvec ", env->stvec);
+ if (riscv_has_ext(env, RVH)) {
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vstvec ", env->vstvec);
+ }
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mepc ", env->mepc);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sepc ", env->sepc);
+ if (riscv_has_ext(env, RVH)) {
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsepc ", env->vsepc);
+ }
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcause ", env->mcause);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "scause ", env->scause);
+ if (riscv_has_ext(env, RVH)) {
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause);
+ }
#endif
for (i = 0; i < 32; i++) {
--
2.23.0
next prev parent reply other threads:[~2019-10-26 0:41 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-25 23:23 [PATCH v2 00/27] Add RISC-V Hypervisor Extension v0.4 Alistair Francis
2019-10-25 23:23 ` [PATCH v2 01/27] target/riscv: Don't set write permissions on dirty PTEs Alistair Francis
2019-10-25 23:23 ` [PATCH v2 02/27] target/riscv: Add the Hypervisor extension Alistair Francis
2019-10-25 23:23 ` [PATCH v2 03/27] target/riscv: Add the virtulisation mode Alistair Francis
2019-10-25 23:23 ` [PATCH v2 04/27] target/riscv: Add the force HS exception mode Alistair Francis
2019-10-25 23:23 ` [PATCH v2 05/27] target/riscv: Fix CSR perm checking for HS mode Alistair Francis
2019-10-25 23:23 ` [PATCH v2 06/27] target/riscv: Add the Hypervisor CSRs to CPUState Alistair Francis
2019-10-25 23:23 ` [PATCH v2 07/27] target/riscv: Print priv and virt in disas log Alistair Francis
2019-10-25 23:23 ` Alistair Francis [this message]
2019-10-25 23:23 ` [PATCH v2 09/27] target/riscv: Add Hypervisor CSR access functions Alistair Francis
2019-10-25 23:23 ` [PATCH v2 10/27] target/riscv: Add Hypervisor virtual CSRs accesses Alistair Francis
2019-10-25 23:23 ` [PATCH v2 11/27] target/riscv: Convert mie and mstatus to pointers Alistair Francis
2019-10-25 23:23 ` [PATCH v2 12/27] target/riscv: Add virtual register swapping function Alistair Francis
2019-10-25 23:23 ` [PATCH v2 13/27] target/riscv: Add support for virtual interrupt setting Alistair Francis
2019-10-25 23:23 ` [PATCH v2 14/27] target/ricsv: Flush the TLB on virtulisation mode changes Alistair Francis
2019-10-25 23:24 ` [PATCH v2 15/27] target/riscv: Generate illegal instruction on WFI when V=1 Alistair Francis
2019-10-25 23:24 ` [PATCH v2 16/27] riscv: plic: Always set sip.SEIP bit for HS Alistair Francis
2019-10-25 23:24 ` [PATCH v2 17/27] target/riscv: Add hypvervisor trap support Alistair Francis
2019-10-25 23:24 ` [PATCH v2 18/27] target/riscv: Add Hypervisor trap return support Alistair Francis
2019-10-25 23:24 ` [PATCH v2 19/27] target/riscv: Add hfence instructions Alistair Francis
2019-10-25 23:24 ` [PATCH v2 20/27] target/riscv: Disable guest FP support based on virtual status Alistair Francis
2019-10-25 23:24 ` [PATCH v2 21/27] target/riscv: Mark both sstatus and vsstatus as dirty Alistair Francis
2019-10-25 23:24 ` [PATCH v2 22/27] target/riscv: Respect MPRV and SPRV for floating point ops Alistair Francis
2019-10-25 23:24 ` [PATCH v2 23/27] target/riscv: Allow specifying MMU stage Alistair Francis
2019-10-25 23:24 ` [PATCH v2 24/27] target/riscv: Implement second stage MMU Alistair Francis
2019-10-25 23:24 ` [PATCH v2 25/27] target/riscv: Add support for the 32-bit MSTATUSH CSR Alistair Francis
2019-10-25 23:24 ` [PATCH v2 26/27] target/riscv: Add the MSTATUS_MPV_ISSET helper macro Alistair Francis
2019-10-25 23:24 ` [PATCH v2 27/27] target/riscv: Allow enabling the Hypervisor extension Alistair Francis
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