* [RFC PATCH v4 00/19] single-binary: Make hw/arm/ common
@ 2025-04-22 14:54 Philippe Mathieu-Daudé
2025-04-22 14:54 ` [RFC PATCH v4 01/19] qapi: Rename TargetInfo structure as QemuTargetInfo Philippe Mathieu-Daudé
` (18 more replies)
0 siblings, 19 replies; 66+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-04-22 14:54 UTC (permalink / raw)
To: qemu-devel, Pierrick Bouvier; +Cc: Richard Henderson, Anton Johansson
Since v3
- QAPI structure renamed as QemuTargetInfo
- MachineClass::get_valid_cpu_types() runtime
- target_aarch64() checking SysEmuTarget value
- Remove CONFIG_TCG #ifdef'ry in hw/arm/
Since v2:
- More comments from Pierrick addressed
- Use GList to register valid CPUs list
- Remove all TARGET_AARCH64 uses in hw/arm/
Since v1:
- Dropped unrelated / irrelevant patches
- Addressed Pierrick comments
- Added R-b tag
- Only considering machines, not CPUs.
Hi,
At this point this series is mostly a draft for Pierrick.
After introducing the generic TargetInfo API [*], we implement
the ARM variants, then use the API to remove target-specific code,
allowing to eventually remove the target-specific arm_ss[] source
set in meson.build, having all objects in arm_common_ss[].
Regards,
Phil.
Available here, based on tcg-next:
https://gitlab.com/philmd/qemu/-/tags/single-binary-hw-arm-rfc-v4
Philippe Mathieu-Daudé (19):
qapi: Rename TargetInfo structure as QemuTargetInfo
qemu: Convert target_name() to TargetInfo API
system/vl: Filter machine list available for a particular target
binary
hw/arm: Register TYPE_TARGET_ARM/AARCH64_MACHINE QOM interfaces
hw/core: Allow ARM/Aarch64 binaries to use the 'none' machine
hw/arm: Filter machine types for qemu-system-arm/aarch64 binaries
meson: Prepare to accept per-binary TargetInfo structure
implementation
config/target: Implement per-binary TargetInfo structure (ARM,
AARCH64)
hw/arm/aspeed: Build objects once
hw/arm/raspi: Build objects once
hw/core/machine: Allow dynamic registration of valid CPU types
hw/arm/virt: Register valid CPU types dynamically
hw/arm/virt: Check accelerator availability at runtime
qemu/target_info: Add %target_arch field to TargetInfo
qemu/target_info: Add target_aarch64() helper
hw/arm/virt: Replace TARGET_AARCH64 -> target_aarch64()
hw/core: Get default_cpu_type calling machine_class_default_cpu_type()
hw/core: Introduce MachineClass::get_default_cpu_type() helper
hw/arm/virt: Get default CPU type at runtime
MAINTAINERS | 8 +++
meson.build | 11 +++
qapi/machine.json | 10 +--
include/hw/arm/machines-qom.h | 18 +++++
include/hw/boards.h | 10 +++
include/hw/core/cpu.h | 2 -
include/qemu/target-info-impl.h | 35 +++++++++
include/qemu/target-info.h | 34 +++++++++
configs/targets/aarch64-softmmu.c | 23 ++++++
configs/targets/arm-softmmu.c | 23 ++++++
cpu-target.c | 5 --
hw/arm/aspeed.c | 115 ++++++++++++++++++++++++++++--
hw/arm/b-l475e-iot01a.c | 6 ++
hw/arm/bananapi_m2u.c | 6 ++
hw/arm/bcm2836.c | 5 +-
hw/arm/collie.c | 6 ++
hw/arm/cubieboard.c | 6 ++
hw/arm/digic_boards.c | 6 ++
hw/arm/exynos4_boards.c | 11 +++
hw/arm/fby35.c | 6 ++
hw/arm/highbank.c | 11 +++
hw/arm/imx25_pdk.c | 6 ++
hw/arm/imx8mp-evk.c | 5 ++
hw/arm/integratorcp.c | 6 ++
hw/arm/kzm.c | 6 ++
hw/arm/mcimx6ul-evk.c | 6 ++
hw/arm/mcimx7d-sabre.c | 6 ++
hw/arm/microbit.c | 6 ++
hw/arm/mps2-tz.c | 21 ++++++
hw/arm/mps2.c | 21 ++++++
hw/arm/mps3r.c | 6 ++
hw/arm/msf2-som.c | 6 ++
hw/arm/musca.c | 11 +++
hw/arm/musicpal.c | 6 ++
hw/arm/netduino2.c | 6 ++
hw/arm/netduinoplus2.c | 6 ++
hw/arm/npcm7xx_boards.c | 26 +++++++
hw/arm/npcm8xx_boards.c | 5 ++
hw/arm/olimex-stm32-h405.c | 6 ++
hw/arm/omap_sx1.c | 11 +++
hw/arm/orangepi.c | 6 ++
hw/arm/raspi.c | 28 ++++++--
hw/arm/raspi4b.c | 5 ++
hw/arm/realview.c | 21 ++++++
hw/arm/sabrelite.c | 6 ++
hw/arm/sbsa-ref.c | 5 ++
hw/arm/stellaris.c | 11 +++
hw/arm/stm32vldiscovery.c | 6 ++
hw/arm/versatilepb.c | 11 +++
hw/arm/vexpress.c | 11 +++
hw/arm/virt.c | 78 +++++++++++---------
hw/arm/xilinx_zynq.c | 6 ++
hw/arm/xlnx-versal-virt.c | 5 ++
hw/arm/xlnx-zcu102.c | 5 ++
hw/core/machine-qmp-cmds.c | 10 +--
hw/core/machine.c | 37 ++++++++++
hw/core/null-machine.c | 6 ++
plugins/loader.c | 2 +-
system/vl.c | 7 +-
target-info-qom.c | 24 +++++++
target-info-stub.c | 22 ++++++
target-info.c | 26 +++++++
target/ppc/cpu_init.c | 2 +-
configs/targets/meson.build | 3 +
hw/arm/meson.build | 12 ++--
65 files changed, 813 insertions(+), 71 deletions(-)
create mode 100644 include/hw/arm/machines-qom.h
create mode 100644 include/qemu/target-info-impl.h
create mode 100644 include/qemu/target-info.h
create mode 100644 configs/targets/aarch64-softmmu.c
create mode 100644 configs/targets/arm-softmmu.c
create mode 100644 target-info-qom.c
create mode 100644 target-info-stub.c
create mode 100644 target-info.c
create mode 100644 configs/targets/meson.build
--
2.47.1
^ permalink raw reply [flat|nested] 66+ messages in thread* [RFC PATCH v4 01/19] qapi: Rename TargetInfo structure as QemuTargetInfo 2025-04-22 14:54 [RFC PATCH v4 00/19] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé @ 2025-04-22 14:54 ` Philippe Mathieu-Daudé 2025-04-22 14:57 ` Philippe Mathieu-Daudé 2025-04-22 17:33 ` Markus Armbruster 2025-04-22 14:54 ` [RFC PATCH v4 02/19] qemu: Convert target_name() to TargetInfo API Philippe Mathieu-Daudé ` (17 subsequent siblings) 18 siblings, 2 replies; 66+ messages in thread From: Philippe Mathieu-Daudé @ 2025-04-22 14:54 UTC (permalink / raw) To: qemu-devel, Pierrick Bouvier; +Cc: Richard Henderson, Anton Johansson The QAPI-generated 'TargetInfo' structure name is only used in a single file. We want to heavily use another structure similarly named. Rename the QAPI one, since structure names are not part of the public API. Suggested-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> --- qapi/machine.json | 10 +++++----- hw/core/machine-qmp-cmds.c | 4 ++-- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/qapi/machine.json b/qapi/machine.json index a6b8795b09e..6889cba2c75 100644 --- a/qapi/machine.json +++ b/qapi/machine.json @@ -275,15 +275,15 @@ { 'command': 'query-current-machine', 'returns': 'CurrentMachineParams' } ## -# @TargetInfo: +# @QemuTargetInfo: # -# Information describing the QEMU target. +# Information on the target configuration built into the QEMU binary. # # @arch: the target architecture # # Since: 1.2 ## -{ 'struct': 'TargetInfo', +{ 'struct': 'QemuTargetInfo', 'data': { 'arch': 'SysEmuTarget' } } ## @@ -291,11 +291,11 @@ # # Return information about the target for this QEMU # -# Returns: TargetInfo +# Returns: QemuTargetInfo # # Since: 1.2 ## -{ 'command': 'query-target', 'returns': 'TargetInfo' } +{ 'command': 'query-target', 'returns': 'QemuTargetInfo' } ## # @UuidInfo: diff --git a/hw/core/machine-qmp-cmds.c b/hw/core/machine-qmp-cmds.c index 3130c5cd456..0e9ca1b90e2 100644 --- a/hw/core/machine-qmp-cmds.c +++ b/hw/core/machine-qmp-cmds.c @@ -132,9 +132,9 @@ CurrentMachineParams *qmp_query_current_machine(Error **errp) return params; } -TargetInfo *qmp_query_target(Error **errp) +QemuTargetInfo *qmp_query_target(Error **errp) { - TargetInfo *info = g_malloc0(sizeof(*info)); + QemuTargetInfo *info = g_malloc0(sizeof(*info)); info->arch = qapi_enum_parse(&SysEmuTarget_lookup, target_name(), -1, &error_abort); -- 2.47.1 ^ permalink raw reply related [flat|nested] 66+ messages in thread
* Re: [RFC PATCH v4 01/19] qapi: Rename TargetInfo structure as QemuTargetInfo 2025-04-22 14:54 ` [RFC PATCH v4 01/19] qapi: Rename TargetInfo structure as QemuTargetInfo Philippe Mathieu-Daudé @ 2025-04-22 14:57 ` Philippe Mathieu-Daudé 2025-04-22 17:33 ` Markus Armbruster 1 sibling, 0 replies; 66+ messages in thread From: Philippe Mathieu-Daudé @ 2025-04-22 14:57 UTC (permalink / raw) To: qemu-devel, Pierrick Bouvier, Markus Armbruster Cc: Richard Henderson, Anton Johansson Cc'ing Markus On 22/4/25 16:54, Philippe Mathieu-Daudé wrote: > The QAPI-generated 'TargetInfo' structure name is only used > in a single file. We want to heavily use another structure > similarly named. Rename the QAPI one, since structure names > are not part of the public API. > > Suggested-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > --- > qapi/machine.json | 10 +++++----- > hw/core/machine-qmp-cmds.c | 4 ++-- > 2 files changed, 7 insertions(+), 7 deletions(-) > > diff --git a/qapi/machine.json b/qapi/machine.json > index a6b8795b09e..6889cba2c75 100644 > --- a/qapi/machine.json > +++ b/qapi/machine.json > @@ -275,15 +275,15 @@ > { 'command': 'query-current-machine', 'returns': 'CurrentMachineParams' } > > ## > -# @TargetInfo: > +# @QemuTargetInfo: > # > -# Information describing the QEMU target. > +# Information on the target configuration built into the QEMU binary. > # > # @arch: the target architecture > # > # Since: 1.2 > ## > -{ 'struct': 'TargetInfo', > +{ 'struct': 'QemuTargetInfo', > 'data': { 'arch': 'SysEmuTarget' } } > > ## > @@ -291,11 +291,11 @@ > # > # Return information about the target for this QEMU > # > -# Returns: TargetInfo > +# Returns: QemuTargetInfo > # > # Since: 1.2 > ## > -{ 'command': 'query-target', 'returns': 'TargetInfo' } > +{ 'command': 'query-target', 'returns': 'QemuTargetInfo' } > > ## > # @UuidInfo: > diff --git a/hw/core/machine-qmp-cmds.c b/hw/core/machine-qmp-cmds.c > index 3130c5cd456..0e9ca1b90e2 100644 > --- a/hw/core/machine-qmp-cmds.c > +++ b/hw/core/machine-qmp-cmds.c > @@ -132,9 +132,9 @@ CurrentMachineParams *qmp_query_current_machine(Error **errp) > return params; > } > > -TargetInfo *qmp_query_target(Error **errp) > +QemuTargetInfo *qmp_query_target(Error **errp) > { > - TargetInfo *info = g_malloc0(sizeof(*info)); > + QemuTargetInfo *info = g_malloc0(sizeof(*info)); > > info->arch = qapi_enum_parse(&SysEmuTarget_lookup, target_name(), -1, > &error_abort); ^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [RFC PATCH v4 01/19] qapi: Rename TargetInfo structure as QemuTargetInfo 2025-04-22 14:54 ` [RFC PATCH v4 01/19] qapi: Rename TargetInfo structure as QemuTargetInfo Philippe Mathieu-Daudé 2025-04-22 14:57 ` Philippe Mathieu-Daudé @ 2025-04-22 17:33 ` Markus Armbruster 1 sibling, 0 replies; 66+ messages in thread From: Markus Armbruster @ 2025-04-22 17:33 UTC (permalink / raw) To: Philippe Mathieu-Daudé Cc: qemu-devel, Pierrick Bouvier, Richard Henderson, Anton Johansson Philippe Mathieu-Daudé <philmd@linaro.org> writes: > The QAPI-generated 'TargetInfo' structure name is only used > in a single file. We want to heavily use another structure > similarly named. Rename the QAPI one, since structure names > are not part of the public API. > > Suggested-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Markus Armbruster <armbru@redhat.com> ^ permalink raw reply [flat|nested] 66+ messages in thread
* [RFC PATCH v4 02/19] qemu: Convert target_name() to TargetInfo API 2025-04-22 14:54 [RFC PATCH v4 00/19] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé 2025-04-22 14:54 ` [RFC PATCH v4 01/19] qapi: Rename TargetInfo structure as QemuTargetInfo Philippe Mathieu-Daudé @ 2025-04-22 14:54 ` Philippe Mathieu-Daudé 2025-04-22 17:27 ` Richard Henderson 2025-04-22 17:28 ` Richard Henderson 2025-04-22 14:54 ` [RFC PATCH v4 03/19] system/vl: Filter machine list available for a particular target binary Philippe Mathieu-Daudé ` (16 subsequent siblings) 18 siblings, 2 replies; 66+ messages in thread From: Philippe Mathieu-Daudé @ 2025-04-22 14:54 UTC (permalink / raw) To: qemu-devel, Pierrick Bouvier; +Cc: Richard Henderson, Anton Johansson Have target_name() be a target-agnostic method, dispatching to a per-target TargetInfo singleton structure. By default a stub singleton is used. No logical change expected. Inspired-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- MAINTAINERS | 7 +++++++ meson.build | 3 +++ include/hw/core/cpu.h | 2 -- include/qemu/target-info-impl.h | 28 ++++++++++++++++++++++++++++ include/qemu/target-info.h | 19 +++++++++++++++++++ cpu-target.c | 5 ----- hw/core/machine-qmp-cmds.c | 1 + plugins/loader.c | 2 +- system/vl.c | 2 +- target-info-stub.c | 19 +++++++++++++++++++ target-info.c | 16 ++++++++++++++++ 11 files changed, 95 insertions(+), 9 deletions(-) create mode 100644 include/qemu/target-info-impl.h create mode 100644 include/qemu/target-info.h create mode 100644 target-info-stub.c create mode 100644 target-info.c diff --git a/MAINTAINERS b/MAINTAINERS index c7083ab1d93..a055f67b5fc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1913,6 +1913,13 @@ F: tests/functional/test_empty_cpu_model.py F: tests/unit/test-smp-parse.c T: git https://gitlab.com/ehabkost/qemu.git machine-next +TargetInfo API +M: Pierrick Bouvier <pierrick.bouvier@linaro.org> +M: Philippe Mathieu-Daudé <philmd@linaro.org> +S: Supported +F: include/qemu/target-info*.h +F: target-info*.c + Xtensa Machines --------------- sim diff --git a/meson.build b/meson.build index bcb9d39a387..09b16e2f7ae 100644 --- a/meson.build +++ b/meson.build @@ -3807,6 +3807,9 @@ endif common_ss.add(pagevary) specific_ss.add(files('page-target.c', 'page-vary-target.c')) +common_ss.add(files('target-info.c')) +specific_ss.add(files('target-info-stub.c')) + subdir('backends') subdir('disas') subdir('migration') diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 5b645df59f5..9d9448341d1 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -1115,8 +1115,6 @@ bool cpu_exec_realizefn(CPUState *cpu, Error **errp); void cpu_exec_unrealizefn(CPUState *cpu); void cpu_exec_reset_hold(CPUState *cpu); -const char *target_name(void); - #ifdef COMPILING_PER_TARGET extern const VMStateDescription vmstate_cpu_common; diff --git a/include/qemu/target-info-impl.h b/include/qemu/target-info-impl.h new file mode 100644 index 00000000000..c276b84ceca --- /dev/null +++ b/include/qemu/target-info-impl.h @@ -0,0 +1,28 @@ +/* + * QEMU TargetInfo structure definition + * + * Copyright (c) Linaro + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef QEMU_TARGET_INFO_IMPL_H +#define QEMU_TARGET_INFO_IMPL_H + +#include "qemu/target-info.h" + +typedef struct TargetInfo { + + /* runtime equivalent of TARGET_NAME definition */ + const char *const target_name; + +} TargetInfo; + +/** + * target_info: + * + * Returns: The TargetInfo structure definition for this target binary. + */ +const TargetInfo *target_info(void); + +#endif diff --git a/include/qemu/target-info.h b/include/qemu/target-info.h new file mode 100644 index 00000000000..1007dc9a5e4 --- /dev/null +++ b/include/qemu/target-info.h @@ -0,0 +1,19 @@ +/* + * QEMU target info API + * + * Copyright (c) Linaro + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef QEMU_TARGET_INFO_H +#define QEMU_TARGET_INFO_H + +/** + * target_name: + * + * Returns: Canonical target name (i.e. "i386"). + */ +const char *target_name(void); + +#endif diff --git a/cpu-target.c b/cpu-target.c index c99d208a7c4..3f82d3ea444 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -165,8 +165,3 @@ bool target_words_bigendian(void) { return TARGET_BIG_ENDIAN; } - -const char *target_name(void) -{ - return TARGET_NAME; -} diff --git a/hw/core/machine-qmp-cmds.c b/hw/core/machine-qmp-cmds.c index 0e9ca1b90e2..529ce8dd9a0 100644 --- a/hw/core/machine-qmp-cmds.c +++ b/hw/core/machine-qmp-cmds.c @@ -19,6 +19,7 @@ #include "qapi/qobject-input-visitor.h" #include "qapi/type-helpers.h" #include "qemu/uuid.h" +#include "qemu/target-info.h" #include "qom/qom-qobject.h" #include "system/hostmem.h" #include "system/hw_accel.h" diff --git a/plugins/loader.c b/plugins/loader.c index 7523d554f03..ccde83414d6 100644 --- a/plugins/loader.c +++ b/plugins/loader.c @@ -29,7 +29,7 @@ #include "qemu/xxhash.h" #include "qemu/plugin.h" #include "qemu/memalign.h" -#include "hw/core/cpu.h" +#include "qemu/target-info.h" #include "exec/tb-flush.h" #include "plugin.h" diff --git a/system/vl.c b/system/vl.c index c17945c4939..cdf6eb9ee49 100644 --- a/system/vl.c +++ b/system/vl.c @@ -40,6 +40,7 @@ #include "qemu/help_option.h" #include "qemu/hw-version.h" #include "qemu/uuid.h" +#include "qemu/target-info.h" #include "system/reset.h" #include "system/runstate.h" #include "system/runstate-action.h" @@ -79,7 +80,6 @@ #include "hw/block/block.h" #include "hw/i386/x86.h" #include "hw/i386/pc.h" -#include "hw/core/cpu.h" #include "migration/cpr.h" #include "migration/misc.h" #include "migration/snapshot.h" diff --git a/target-info-stub.c b/target-info-stub.c new file mode 100644 index 00000000000..076b9254dd0 --- /dev/null +++ b/target-info-stub.c @@ -0,0 +1,19 @@ +/* + * QEMU target info stubs + * + * Copyright (c) Linaro + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/target-info-impl.h" + +static const TargetInfo target_info_stub = { + .target_name = TARGET_NAME, +}; + +const TargetInfo *target_info(void) +{ + return &target_info_stub; +} diff --git a/target-info.c b/target-info.c new file mode 100644 index 00000000000..84b18931e7e --- /dev/null +++ b/target-info.c @@ -0,0 +1,16 @@ +/* + * QEMU target info helpers + * + * Copyright (c) Linaro + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/target-info.h" +#include "qemu/target-info-impl.h" + +const char *target_name(void) +{ + return target_info()->target_name; +} -- 2.47.1 ^ permalink raw reply related [flat|nested] 66+ messages in thread
* Re: [RFC PATCH v4 02/19] qemu: Convert target_name() to TargetInfo API 2025-04-22 14:54 ` [RFC PATCH v4 02/19] qemu: Convert target_name() to TargetInfo API Philippe Mathieu-Daudé @ 2025-04-22 17:27 ` Richard Henderson 2025-04-22 17:28 ` Richard Henderson 1 sibling, 0 replies; 66+ messages in thread From: Richard Henderson @ 2025-04-22 17:27 UTC (permalink / raw) To: Philippe Mathieu-Daudé, qemu-devel, Pierrick Bouvier; +Cc: Anton Johansson On 4/22/25 07:54, Philippe Mathieu-Daudé wrote: > Have target_name() be a target-agnostic method, dispatching > to a per-target TargetInfo singleton structure. > By default a stub singleton is used. No logical change > expected. > > Inspired-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~ ^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [RFC PATCH v4 02/19] qemu: Convert target_name() to TargetInfo API 2025-04-22 14:54 ` [RFC PATCH v4 02/19] qemu: Convert target_name() to TargetInfo API Philippe Mathieu-Daudé 2025-04-22 17:27 ` Richard Henderson @ 2025-04-22 17:28 ` Richard Henderson 1 sibling, 0 replies; 66+ messages in thread From: Richard Henderson @ 2025-04-22 17:28 UTC (permalink / raw) To: Philippe Mathieu-Daudé, qemu-devel, Pierrick Bouvier; +Cc: Anton Johansson On 4/22/25 07:54, Philippe Mathieu-Daudé wrote: > +typedef struct TargetInfo { > + > + /* runtime equivalent of TARGET_NAME definition */ > + const char *const target_name; > + > +} TargetInfo; Watch the extra newlines. r~ ^ permalink raw reply [flat|nested] 66+ messages in thread
* [RFC PATCH v4 03/19] system/vl: Filter machine list available for a particular target binary 2025-04-22 14:54 [RFC PATCH v4 00/19] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé 2025-04-22 14:54 ` [RFC PATCH v4 01/19] qapi: Rename TargetInfo structure as QemuTargetInfo Philippe Mathieu-Daudé 2025-04-22 14:54 ` [RFC PATCH v4 02/19] qemu: Convert target_name() to TargetInfo API Philippe Mathieu-Daudé @ 2025-04-22 14:54 ` Philippe Mathieu-Daudé 2025-04-22 17:29 ` Richard Henderson 2025-04-22 14:54 ` [RFC PATCH v4 04/19] hw/arm: Register TYPE_TARGET_ARM/AARCH64_MACHINE QOM interfaces Philippe Mathieu-Daudé ` (15 subsequent siblings) 18 siblings, 1 reply; 66+ messages in thread From: Philippe Mathieu-Daudé @ 2025-04-22 14:54 UTC (permalink / raw) To: qemu-devel, Pierrick Bouvier; +Cc: Richard Henderson, Anton Johansson Binaries can register a QOM type to filter their machines by filling their TargetInfo::machine_typename field. This can be used by example by main() -> machine_help_func() to filter the machines list. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- meson.build | 1 + include/qemu/target-info-impl.h | 3 +++ include/qemu/target-info.h | 8 ++++++++ system/vl.c | 3 ++- target-info-qom.c | 15 +++++++++++++++ target-info-stub.c | 2 ++ target-info.c | 5 +++++ 7 files changed, 36 insertions(+), 1 deletion(-) create mode 100644 target-info-qom.c diff --git a/meson.build b/meson.build index 09b16e2f7ae..a1109b6db3f 100644 --- a/meson.build +++ b/meson.build @@ -3808,6 +3808,7 @@ common_ss.add(pagevary) specific_ss.add(files('page-target.c', 'page-vary-target.c')) common_ss.add(files('target-info.c')) +system_ss.add(files('target-info-qom.c')) specific_ss.add(files('target-info-stub.c')) subdir('backends') diff --git a/include/qemu/target-info-impl.h b/include/qemu/target-info-impl.h index c276b84ceca..4ef54c5136a 100644 --- a/include/qemu/target-info-impl.h +++ b/include/qemu/target-info-impl.h @@ -16,6 +16,9 @@ typedef struct TargetInfo { /* runtime equivalent of TARGET_NAME definition */ const char *const target_name; + /* QOM typename machines for this binary must implement */ + const char *const machine_typename; + } TargetInfo; /** diff --git a/include/qemu/target-info.h b/include/qemu/target-info.h index 1007dc9a5e4..0224b35b166 100644 --- a/include/qemu/target-info.h +++ b/include/qemu/target-info.h @@ -16,4 +16,12 @@ */ const char *target_name(void); +/** + * target_machine_typename: + * + * Returns: Name of the QOM interface implemented by machines + * usable on this target binary. + */ +const char *target_machine_typename(void); + #endif diff --git a/system/vl.c b/system/vl.c index cdf6eb9ee49..e8706a9ce87 100644 --- a/system/vl.c +++ b/system/vl.c @@ -27,6 +27,7 @@ #include "qemu/datadir.h" #include "qemu/units.h" #include "qemu/module.h" +#include "qemu/target-info.h" #include "exec/cpu-common.h" #include "exec/page-vary.h" #include "hw/qdev-properties.h" @@ -1564,7 +1565,7 @@ static void machine_help_func(const QDict *qdict) GSList *el; const char *type = qdict_get_try_str(qdict, "type"); - machines = object_class_get_list(TYPE_MACHINE, false); + machines = object_class_get_list(target_machine_typename(), false); if (type) { ObjectClass *machine_class = OBJECT_CLASS(find_machine(type, machines)); if (machine_class) { diff --git a/target-info-qom.c b/target-info-qom.c new file mode 100644 index 00000000000..a6fd8f1d5a3 --- /dev/null +++ b/target-info-qom.c @@ -0,0 +1,15 @@ +/* + * QEMU binary/target API (QOM types) + * + * Copyright (c) Linaro + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qom/object.h" + +static const TypeInfo target_info_types[] = { +}; + +DEFINE_TYPES(target_info_types) diff --git a/target-info-stub.c b/target-info-stub.c index 076b9254dd0..218e5898e7f 100644 --- a/target-info-stub.c +++ b/target-info-stub.c @@ -8,9 +8,11 @@ #include "qemu/osdep.h" #include "qemu/target-info-impl.h" +#include "hw/boards.h" static const TargetInfo target_info_stub = { .target_name = TARGET_NAME, + .machine_typename = TYPE_MACHINE, }; const TargetInfo *target_info(void) diff --git a/target-info.c b/target-info.c index 84b18931e7e..0042769e3a2 100644 --- a/target-info.c +++ b/target-info.c @@ -14,3 +14,8 @@ const char *target_name(void) { return target_info()->target_name; } + +const char *target_machine_typename(void) +{ + return target_info()->machine_typename; +} -- 2.47.1 ^ permalink raw reply related [flat|nested] 66+ messages in thread
* Re: [RFC PATCH v4 03/19] system/vl: Filter machine list available for a particular target binary 2025-04-22 14:54 ` [RFC PATCH v4 03/19] system/vl: Filter machine list available for a particular target binary Philippe Mathieu-Daudé @ 2025-04-22 17:29 ` Richard Henderson 0 siblings, 0 replies; 66+ messages in thread From: Richard Henderson @ 2025-04-22 17:29 UTC (permalink / raw) To: Philippe Mathieu-Daudé, qemu-devel, Pierrick Bouvier; +Cc: Anton Johansson On 4/22/25 07:54, Philippe Mathieu-Daudé wrote: > Binaries can register a QOM type to filter their machines > by filling their TargetInfo::machine_typename field. > > This can be used by example by main() -> machine_help_func() > to filter the machines list. > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> > --- > meson.build | 1 + > include/qemu/target-info-impl.h | 3 +++ > include/qemu/target-info.h | 8 ++++++++ > system/vl.c | 3 ++- > target-info-qom.c | 15 +++++++++++++++ > target-info-stub.c | 2 ++ > target-info.c | 5 +++++ > 7 files changed, 36 insertions(+), 1 deletion(-) > create mode 100644 target-info-qom.c > > diff --git a/meson.build b/meson.build > index 09b16e2f7ae..a1109b6db3f 100644 > --- a/meson.build > +++ b/meson.build > @@ -3808,6 +3808,7 @@ common_ss.add(pagevary) > specific_ss.add(files('page-target.c', 'page-vary-target.c')) > > common_ss.add(files('target-info.c')) > +system_ss.add(files('target-info-qom.c')) > specific_ss.add(files('target-info-stub.c')) > > subdir('backends') > diff --git a/include/qemu/target-info-impl.h b/include/qemu/target-info-impl.h > index c276b84ceca..4ef54c5136a 100644 > --- a/include/qemu/target-info-impl.h > +++ b/include/qemu/target-info-impl.h > @@ -16,6 +16,9 @@ typedef struct TargetInfo { > /* runtime equivalent of TARGET_NAME definition */ > const char *const target_name; > > + /* QOM typename machines for this binary must implement */ > + const char *const machine_typename; > + > } TargetInfo; You don't really want the second 'const' in either of these. > diff --git a/target-info-qom.c b/target-info-qom.c > new file mode 100644 > index 00000000000..a6fd8f1d5a3 > --- /dev/null > +++ b/target-info-qom.c > @@ -0,0 +1,15 @@ > +/* > + * QEMU binary/target API (QOM types) > + * > + * Copyright (c) Linaro > + * > + * SPDX-License-Identifier: GPL-2.0-or-later > + */ > + > +#include "qemu/osdep.h" > +#include "qom/object.h" > + > +static const TypeInfo target_info_types[] = { > +}; > + > +DEFINE_TYPES(target_info_types) Delay this until it's actually used. Otherwise, Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~ ^ permalink raw reply [flat|nested] 66+ messages in thread
* [RFC PATCH v4 04/19] hw/arm: Register TYPE_TARGET_ARM/AARCH64_MACHINE QOM interfaces 2025-04-22 14:54 [RFC PATCH v4 00/19] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé ` (2 preceding siblings ...) 2025-04-22 14:54 ` [RFC PATCH v4 03/19] system/vl: Filter machine list available for a particular target binary Philippe Mathieu-Daudé @ 2025-04-22 14:54 ` Philippe Mathieu-Daudé 2025-04-22 17:31 ` Richard Henderson 2025-04-22 14:54 ` [RFC PATCH v4 05/19] hw/core: Allow ARM/Aarch64 binaries to use the 'none' machine Philippe Mathieu-Daudé ` (14 subsequent siblings) 18 siblings, 1 reply; 66+ messages in thread From: Philippe Mathieu-Daudé @ 2025-04-22 14:54 UTC (permalink / raw) To: qemu-devel, Pierrick Bouvier; +Cc: Richard Henderson, Anton Johansson Define the TYPE_TARGET_ARM_MACHINE and TYPE_TARGET_AARCH64_MACHINE QOM interface names to allow machines to implement them. Register these interfaces in common code in target_info-qom.c used by all binaries because QOM interfaces must be registered before being checked (see next commit with the 'none' machine). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- include/hw/arm/machines-qom.h | 18 ++++++++++++++++++ target-info-qom.c | 9 +++++++++ 2 files changed, 27 insertions(+) create mode 100644 include/hw/arm/machines-qom.h diff --git a/include/hw/arm/machines-qom.h b/include/hw/arm/machines-qom.h new file mode 100644 index 00000000000..a17225f5f92 --- /dev/null +++ b/include/hw/arm/machines-qom.h @@ -0,0 +1,18 @@ +/* + * QOM type definitions for ARM / Aarch64 machines + * + * Copyright (c) Linaro + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_ARM_MACHINES_QOM_H +#define HW_ARM_MACHINES_QOM_H + +#define TYPE_TARGET_ARM_MACHINE \ + "target-info-arm-machine" + +#define TYPE_TARGET_AARCH64_MACHINE \ + "target-info-aarch64-machine" + +#endif diff --git a/target-info-qom.c b/target-info-qom.c index a6fd8f1d5a3..7fd58d24818 100644 --- a/target-info-qom.c +++ b/target-info-qom.c @@ -8,8 +8,17 @@ #include "qemu/osdep.h" #include "qom/object.h" +#include "hw/arm/machines-qom.h" static const TypeInfo target_info_types[] = { + { + .name = TYPE_TARGET_ARM_MACHINE, + .parent = TYPE_INTERFACE, + }, + { + .name = TYPE_TARGET_AARCH64_MACHINE, + .parent = TYPE_INTERFACE, + }, }; DEFINE_TYPES(target_info_types) -- 2.47.1 ^ permalink raw reply related [flat|nested] 66+ messages in thread
* Re: [RFC PATCH v4 04/19] hw/arm: Register TYPE_TARGET_ARM/AARCH64_MACHINE QOM interfaces 2025-04-22 14:54 ` [RFC PATCH v4 04/19] hw/arm: Register TYPE_TARGET_ARM/AARCH64_MACHINE QOM interfaces Philippe Mathieu-Daudé @ 2025-04-22 17:31 ` Richard Henderson 0 siblings, 0 replies; 66+ messages in thread From: Richard Henderson @ 2025-04-22 17:31 UTC (permalink / raw) To: Philippe Mathieu-Daudé, qemu-devel, Pierrick Bouvier; +Cc: Anton Johansson On 4/22/25 07:54, Philippe Mathieu-Daudé wrote: > Define the TYPE_TARGET_ARM_MACHINE and TYPE_TARGET_AARCH64_MACHINE > QOM interface names to allow machines to implement them. > > Register these interfaces in common code in target_info-qom.c used > by all binaries because QOM interfaces must be registered before > being checked (see next commit with the 'none' machine). > > Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org> > Reviewed-by: Pierrick Bouvier<pierrick.bouvier@linaro.org> > --- > include/hw/arm/machines-qom.h | 18 ++++++++++++++++++ > target-info-qom.c | 9 +++++++++ > 2 files changed, 27 insertions(+) > create mode 100644 include/hw/arm/machines-qom.h Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~ ^ permalink raw reply [flat|nested] 66+ messages in thread
* [RFC PATCH v4 05/19] hw/core: Allow ARM/Aarch64 binaries to use the 'none' machine 2025-04-22 14:54 [RFC PATCH v4 00/19] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé ` (3 preceding siblings ...) 2025-04-22 14:54 ` [RFC PATCH v4 04/19] hw/arm: Register TYPE_TARGET_ARM/AARCH64_MACHINE QOM interfaces Philippe Mathieu-Daudé @ 2025-04-22 14:54 ` Philippe Mathieu-Daudé 2025-04-22 17:34 ` Richard Henderson 2025-04-22 14:54 ` [RFC PATCH v4 06/19] hw/arm: Filter machine types for qemu-system-arm/aarch64 binaries Philippe Mathieu-Daudé ` (13 subsequent siblings) 18 siblings, 1 reply; 66+ messages in thread From: Philippe Mathieu-Daudé @ 2025-04-22 14:54 UTC (permalink / raw) To: qemu-devel, Pierrick Bouvier; +Cc: Richard Henderson, Anton Johansson When we'll start to use target_machine_typename() to filter machines for the ARM/Aarch64 binaries, the 'none' machine will be filtered out. Register the proper interfaces to keep it available. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- hw/core/null-machine.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/hw/core/null-machine.c b/hw/core/null-machine.c index 1ccaf652eb4..dd56d7cb7e5 100644 --- a/hw/core/null-machine.c +++ b/hw/core/null-machine.c @@ -16,6 +16,7 @@ #include "hw/boards.h" #include "system/address-spaces.h" #include "hw/core/cpu.h" +#include "hw/arm/machines-qom.h" static void machine_none_init(MachineState *mch) { @@ -62,6 +63,11 @@ static const TypeInfo null_machine_types[] = { .name = MACHINE_TYPE_NAME("none"), .parent = TYPE_MACHINE, .class_init = null_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; -- 2.47.1 ^ permalink raw reply related [flat|nested] 66+ messages in thread
* Re: [RFC PATCH v4 05/19] hw/core: Allow ARM/Aarch64 binaries to use the 'none' machine 2025-04-22 14:54 ` [RFC PATCH v4 05/19] hw/core: Allow ARM/Aarch64 binaries to use the 'none' machine Philippe Mathieu-Daudé @ 2025-04-22 17:34 ` Richard Henderson 0 siblings, 0 replies; 66+ messages in thread From: Richard Henderson @ 2025-04-22 17:34 UTC (permalink / raw) To: Philippe Mathieu-Daudé, qemu-devel, Pierrick Bouvier; +Cc: Anton Johansson On 4/22/25 07:54, Philippe Mathieu-Daudé wrote: > When we'll start to use target_machine_typename() to filter > machines for the ARM/Aarch64 binaries, the 'none' machine > will be filtered out. Register the proper interfaces to keep > it available. Perhaps "would be filtered"? > @@ -62,6 +63,11 @@ static const TypeInfo null_machine_types[] = { > .name = MACHINE_TYPE_NAME("none"), > .parent = TYPE_MACHINE, > .class_init = null_machine_class_init, > + .interfaces = (InterfaceInfo[]) { > + { TYPE_TARGET_ARM_MACHINE }, > + { TYPE_TARGET_AARCH64_MACHINE }, > + { }, > + }, I presume this list will continue to grow. Perhaps sort alphabetically. r~ ^ permalink raw reply [flat|nested] 66+ messages in thread
* [RFC PATCH v4 06/19] hw/arm: Filter machine types for qemu-system-arm/aarch64 binaries 2025-04-22 14:54 [RFC PATCH v4 00/19] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé ` (4 preceding siblings ...) 2025-04-22 14:54 ` [RFC PATCH v4 05/19] hw/core: Allow ARM/Aarch64 binaries to use the 'none' machine Philippe Mathieu-Daudé @ 2025-04-22 14:54 ` Philippe Mathieu-Daudé 2025-04-22 17:40 ` Richard Henderson 2025-04-22 14:54 ` [RFC PATCH v4 07/19] meson: Prepare to accept per-binary TargetInfo structure implementation Philippe Mathieu-Daudé ` (12 subsequent siblings) 18 siblings, 1 reply; 66+ messages in thread From: Philippe Mathieu-Daudé @ 2025-04-22 14:54 UTC (permalink / raw) To: qemu-devel, Pierrick Bouvier; +Cc: Richard Henderson, Anton Johansson Since the qemu-system-aarch64 binary is able to run all machines indistinctly, simply register the TYPE_TARGET_AARCH64_MACHINE interface for all existing machines under the hw/arm/ directory. Very few machines are restricted to the qemu-system-aarch64 binary: $ git grep TARGET_AARCH64 hw/arm/meson.build hw/arm/meson.build:31:arm_common_ss.add(when: ['CONFIG_RASPI', 'TARGET_AARCH64'], if_true: files('bcm2838.c', 'raspi4b.c')) hw/arm/meson.build:50:arm_common_ss.add(when: ['CONFIG_ASPEED_SOC', 'TARGET_AARCH64'], if_true: files('aspeed_ast27x0.c')) $ git grep -W AARCH64 hw/arm/Kconfig hw/arm/Kconfig=185=config SBSA_REF hw/arm/Kconfig-186- bool hw/arm/Kconfig-187- default y hw/arm/Kconfig:188: depends on TCG && AARCH64 -- hw/arm/Kconfig=413=config XLNX_ZYNQMP_ARM hw/arm/Kconfig-414- bool hw/arm/Kconfig-415- default y if PIXMAN hw/arm/Kconfig:416: depends on TCG && AARCH64 -- hw/arm/Kconfig=435=config XLNX_VERSAL hw/arm/Kconfig-436- bool hw/arm/Kconfig-437- default y hw/arm/Kconfig:438: depends on TCG && AARCH64 -- hw/arm/Kconfig=475=config NPCM8XX hw/arm/Kconfig-476- bool hw/arm/Kconfig-477- default y hw/arm/Kconfig:478: depends on TCG && AARCH64 -- hw/arm/Kconfig=605=config FSL_IMX8MP_EVK hw/arm/Kconfig-606- bool hw/arm/Kconfig-607- default y hw/arm/Kconfig:608: depends on TCG && AARCH64 $ git grep -wW TARGET_AARCH64 hw/arm | fgrep -4 MACHINE_TYPE_NAME ... hw/arm/aspeed.c:1939:#ifdef TARGET_AARCH64 hw/arm/aspeed.c-1940- }, { hw/arm/aspeed.c-1941- .name = MACHINE_TYPE_NAME("ast2700a0-evb"), hw/arm/aspeed.c-1949- .name = MACHINE_TYPE_NAME("ast2700a1-evb"), hw/arm/raspi.c:420:#ifdef TARGET_AARCH64 hw/arm/raspi.c-421- }, { hw/arm/raspi.c-422- .name = MACHINE_TYPE_NAME("raspi3ap"), hw/arm/raspi.c-429- }, { hw/arm/raspi.c-430- .name = MACHINE_TYPE_NAME("raspi3b"), This can be verified as: $ diff -u0 <(qemu-system-arm -M help) <(qemu-system-aarch64 -M help) @@ -5,3 +4,0 @@ -ast2700-evb Aspeed AST2700 A0 EVB (Cortex-A35) (alias of ast2700a0-evb) -ast2700a0-evb Aspeed AST2700 A0 EVB (Cortex-A35) -ast2700a1-evb Aspeed AST2700 A1 EVB (Cortex-A35) @@ -22 +18,0 @@ -imx8mp-evk NXP i.MX 8M Plus EVK Board @@ -49 +44,0 @@ -npcm845-evb Nuvoton NPCM845 Evaluation Board (Cortex-A35) @@ -63,3 +57,0 @@ -raspi3ap Raspberry Pi 3A+ (revision 1.0) -raspi3b Raspberry Pi 3B (revision 1.2) -raspi4b Raspberry Pi 4B (revision 1.5) @@ -72 +63,0 @@ -sbsa-ref QEMU 'SBSA Reference' ARM Virtual Machine @@ -116,2 +106,0 @@ -xlnx-versal-virt Xilinx Versal Virtual development board -xlnx-zcu102 Xilinx ZynqMP ZCU102 board with 4xA53s and 2xR5Fs based on the value of smp Register the TYPE_TARGET_ARM_MACHINE interface for all the machines not listed previously. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- hw/arm/aspeed.c | 109 +++++++++++++++++++++++++++++++++++++ hw/arm/b-l475e-iot01a.c | 6 ++ hw/arm/bananapi_m2u.c | 6 ++ hw/arm/bcm2836.c | 1 + hw/arm/collie.c | 6 ++ hw/arm/cubieboard.c | 6 ++ hw/arm/digic_boards.c | 6 ++ hw/arm/exynos4_boards.c | 11 ++++ hw/arm/fby35.c | 6 ++ hw/arm/highbank.c | 11 ++++ hw/arm/imx25_pdk.c | 6 ++ hw/arm/imx8mp-evk.c | 5 ++ hw/arm/integratorcp.c | 6 ++ hw/arm/kzm.c | 6 ++ hw/arm/mcimx6ul-evk.c | 6 ++ hw/arm/mcimx7d-sabre.c | 6 ++ hw/arm/microbit.c | 6 ++ hw/arm/mps2-tz.c | 21 +++++++ hw/arm/mps2.c | 21 +++++++ hw/arm/mps3r.c | 6 ++ hw/arm/msf2-som.c | 6 ++ hw/arm/musca.c | 11 ++++ hw/arm/musicpal.c | 6 ++ hw/arm/netduino2.c | 6 ++ hw/arm/netduinoplus2.c | 6 ++ hw/arm/npcm7xx_boards.c | 26 +++++++++ hw/arm/npcm8xx_boards.c | 5 ++ hw/arm/olimex-stm32-h405.c | 6 ++ hw/arm/omap_sx1.c | 11 ++++ hw/arm/orangepi.c | 6 ++ hw/arm/raspi.c | 24 ++++++++ hw/arm/raspi4b.c | 5 ++ hw/arm/realview.c | 21 +++++++ hw/arm/sabrelite.c | 6 ++ hw/arm/sbsa-ref.c | 5 ++ hw/arm/stellaris.c | 11 ++++ hw/arm/stm32vldiscovery.c | 6 ++ hw/arm/versatilepb.c | 11 ++++ hw/arm/vexpress.c | 11 ++++ hw/arm/virt.c | 6 ++ hw/arm/xilinx_zynq.c | 6 ++ hw/arm/xlnx-versal-virt.c | 5 ++ hw/arm/xlnx-zcu102.c | 5 ++ 43 files changed, 468 insertions(+) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 82f42582fa3..ce4d49a9f59 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -15,6 +15,7 @@ #include "hw/arm/aspeed.h" #include "hw/arm/aspeed_soc.h" #include "hw/arm/aspeed_eeprom.h" +#include "hw/arm/machines-qom.h" #include "hw/block/flash.h" #include "hw/i2c/i2c_mux_pca954x.h" #include "hw/i2c/smbus_eeprom.h" @@ -1760,91 +1761,199 @@ static const TypeInfo aspeed_machine_types[] = { .name = MACHINE_TYPE_NAME("palmetto-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_palmetto_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("supermicrox11-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_supermicrox11_bmc_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("supermicro-x11spi-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_supermicro_x11spi_bmc_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("ast2500-evb"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_ast2500_evb_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("romulus-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_romulus_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("sonorapass-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_sonorapass_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("witherspoon-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_witherspoon_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("ast2600-evb"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_ast2600_evb_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("yosemitev2-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_yosemitev2_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("tiogapass-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_tiogapass_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("g220a-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_g220a_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("qcom-dc-scm-v1-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_qcom_dc_scm_v1_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("qcom-firework-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_qcom_firework_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("fp5280g2-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_fp5280g2_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("quanta-q71l-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_quanta_q71l_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("rainier-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_rainier_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("fuji-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_fuji_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("bletchley-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_bletchley_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("fby35-bmc"), .parent = MACHINE_TYPE_NAME("ast2600-evb"), .class_init = aspeed_machine_fby35_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("ast1030-evb"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_minibmc_machine_ast1030_evb_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, #ifdef TARGET_AARCH64 }, { .name = MACHINE_TYPE_NAME("ast2700a0-evb"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_ast2700a0_evb_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("ast2700a1-evb"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_ast2700a1_evb_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, #endif }, { .name = TYPE_ASPEED_MACHINE, diff --git a/hw/arm/b-l475e-iot01a.c b/hw/arm/b-l475e-iot01a.c index c9a5209216c..7af7db3dbb3 100644 --- a/hw/arm/b-l475e-iot01a.c +++ b/hw/arm/b-l475e-iot01a.c @@ -29,6 +29,7 @@ #include "qemu/error-report.h" #include "hw/arm/boot.h" #include "hw/core/split-irq.h" +#include "hw/arm/machines-qom.h" #include "hw/arm/stm32l4x5_soc.h" #include "hw/gpio/stm32l4x5_gpio.h" #include "hw/display/dm163.h" @@ -131,6 +132,11 @@ static const TypeInfo bl475e_machine_type[] = { .parent = TYPE_MACHINE, .instance_size = sizeof(Bl475eMachineState), .class_init = bl475e_machine_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, } }; diff --git a/hw/arm/bananapi_m2u.c b/hw/arm/bananapi_m2u.c index 724ee4b05e5..5104a45390b 100644 --- a/hw/arm/bananapi_m2u.c +++ b/hw/arm/bananapi_m2u.c @@ -27,6 +27,7 @@ #include "hw/qdev-properties.h" #include "hw/arm/allwinner-r40.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" static struct arm_boot_info bpim2u_binfo; @@ -150,6 +151,11 @@ static const TypeInfo bananapi_machine_types[] = { .name = MACHINE_TYPE_NAME("bpim2u"), .parent = TYPE_MACHINE, .class_init = bpim2u_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index 95e16806fa1..f60489983ba 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -14,6 +14,7 @@ #include "qemu/module.h" #include "hw/arm/bcm2836.h" #include "hw/arm/raspi_platform.h" +#include "hw/arm/machines-qom.h" #include "hw/sysbus.h" #include "target/arm/cpu-qom.h" #include "target/arm/gtimer.h" diff --git a/hw/arm/collie.c b/hw/arm/collie.c index e83aee58c6b..458ed53f0f6 100644 --- a/hw/arm/collie.c +++ b/hw/arm/collie.c @@ -15,6 +15,7 @@ #include "hw/boards.h" #include "strongarm.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "hw/block/flash.h" #include "system/address-spaces.h" #include "qom/object.h" @@ -86,6 +87,11 @@ static const TypeInfo collie_machine_typeinfo = { .parent = TYPE_MACHINE, .class_init = collie_machine_class_init, .instance_size = sizeof(CollieMachineState), + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void collie_machine_register_types(void) diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c index 36062ac7037..00656169b72 100644 --- a/hw/arm/cubieboard.c +++ b/hw/arm/cubieboard.c @@ -22,6 +22,7 @@ #include "hw/qdev-properties.h" #include "hw/arm/allwinner-a10.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "hw/i2c/i2c.h" static struct arm_boot_info cubieboard_binfo = { @@ -131,6 +132,11 @@ static const TypeInfo cubieboard_machine_types[] = { .name = MACHINE_TYPE_NAME("cubieboard"), .parent = TYPE_MACHINE, .class_init = cubieboard_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c index 3c0cc6e4370..7b9fbb5524b 100644 --- a/hw/arm/digic_boards.c +++ b/hw/arm/digic_boards.c @@ -29,6 +29,7 @@ #include "hw/boards.h" #include "qemu/error-report.h" #include "hw/arm/digic.h" +#include "hw/arm/machines-qom.h" #include "hw/block/flash.h" #include "hw/loader.h" #include "system/qtest.h" @@ -152,6 +153,11 @@ static const TypeInfo digic_machine_types[] = { .name = MACHINE_TYPE_NAME("canon-a1100"), .parent = TYPE_MACHINE, .class_init = digic_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c index 2d8f2d73265..71601a0d6f0 100644 --- a/hw/arm/exynos4_boards.c +++ b/hw/arm/exynos4_boards.c @@ -28,6 +28,7 @@ #include "hw/sysbus.h" #include "net/net.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "system/address-spaces.h" #include "hw/arm/exynos4210.h" #include "hw/net/lan9118.h" @@ -172,6 +173,11 @@ static const TypeInfo nuri_type = { .name = MACHINE_TYPE_NAME("nuri"), .parent = TYPE_MACHINE, .class_init = nuri_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void smdkc210_class_init(ObjectClass *oc, void *data) @@ -192,6 +198,11 @@ static const TypeInfo smdkc210_type = { .name = MACHINE_TYPE_NAME("smdkc210"), .parent = TYPE_MACHINE, .class_init = smdkc210_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void exynos4_machines_init(void) diff --git a/hw/arm/fby35.c b/hw/arm/fby35.c index 6d3663f14a1..84b65844b34 100644 --- a/hw/arm/fby35.c +++ b/hw/arm/fby35.c @@ -14,6 +14,7 @@ #include "hw/qdev-clock.h" #include "hw/arm/aspeed_soc.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #define TYPE_FBY35 MACHINE_TYPE_NAME("fby35") OBJECT_DECLARE_SIMPLE_TYPE(Fby35State, FBY35); @@ -187,6 +188,11 @@ static const TypeInfo fby35_types[] = { .class_init = fby35_class_init, .instance_size = sizeof(Fby35State), .instance_init = fby35_instance_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c index 0f3c207d548..d26346ea8ad 100644 --- a/hw/arm/highbank.c +++ b/hw/arm/highbank.c @@ -23,6 +23,7 @@ #include "hw/sysbus.h" #include "migration/vmstate.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "hw/loader.h" #include "net/net.h" #include "system/runstate.h" @@ -363,6 +364,11 @@ static const TypeInfo highbank_type = { .name = MACHINE_TYPE_NAME("highbank"), .parent = TYPE_MACHINE, .class_init = highbank_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void midway_class_init(ObjectClass *oc, void *data) @@ -387,6 +393,11 @@ static const TypeInfo midway_type = { .name = MACHINE_TYPE_NAME("midway"), .parent = TYPE_MACHINE, .class_init = midway_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void calxeda_machines_init(void) diff --git a/hw/arm/imx25_pdk.c b/hw/arm/imx25_pdk.c index a90def7f1a2..86f0855c929 100644 --- a/hw/arm/imx25_pdk.c +++ b/hw/arm/imx25_pdk.c @@ -28,6 +28,7 @@ #include "hw/qdev-properties.h" #include "hw/arm/fsl-imx25.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "hw/boards.h" #include "qemu/error-report.h" #include "system/qtest.h" @@ -157,6 +158,11 @@ static const TypeInfo imx25_machine_types[] = { .name = MACHINE_TYPE_NAME("imx25-pdk"), .parent = TYPE_MACHINE, .class_init = imx25_pdk_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/imx8mp-evk.c b/hw/arm/imx8mp-evk.c index c7d87d99230..44f704b9bd3 100644 --- a/hw/arm/imx8mp-evk.c +++ b/hw/arm/imx8mp-evk.c @@ -10,6 +10,7 @@ #include "system/address-spaces.h" #include "hw/arm/boot.h" #include "hw/arm/fsl-imx8mp.h" +#include "hw/arm/machines-qom.h" #include "hw/boards.h" #include "hw/qdev-properties.h" #include "system/qtest.h" @@ -79,6 +80,10 @@ static const TypeInfo imx8_machine_types[] = { .name = MACHINE_TYPE_NAME("imx8mp-evk"), .parent = TYPE_MACHINE, .class_init = imx8mp_evk_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c index f95916b517d..efe1075ecc0 100644 --- a/hw/arm/integratorcp.c +++ b/hw/arm/integratorcp.c @@ -13,6 +13,7 @@ #include "migration/vmstate.h" #include "hw/boards.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "hw/misc/arm_integrator_debug.h" #include "hw/net/smc91c111.h" #include "net/net.h" @@ -760,6 +761,11 @@ static const TypeInfo integratorcp_machine_types[] = { .name = MACHINE_TYPE_NAME("integratorcp"), .parent = TYPE_MACHINE, .class_init = integratorcp_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/kzm.c b/hw/arm/kzm.c index b56cabe9f94..02ece3c0139 100644 --- a/hw/arm/kzm.c +++ b/hw/arm/kzm.c @@ -17,6 +17,7 @@ #include "qapi/error.h" #include "hw/arm/fsl-imx31.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "hw/boards.h" #include "qemu/error-report.h" #include "system/address-spaces.h" @@ -146,6 +147,11 @@ static const TypeInfo kzm_machine_types[] = { .name = MACHINE_TYPE_NAME("kzm"), .parent = TYPE_MACHINE, .class_init = kzm_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/mcimx6ul-evk.c b/hw/arm/mcimx6ul-evk.c index d947836d2be..ea636fa2e7c 100644 --- a/hw/arm/mcimx6ul-evk.c +++ b/hw/arm/mcimx6ul-evk.c @@ -14,6 +14,7 @@ #include "qapi/error.h" #include "hw/arm/fsl-imx6ul.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "hw/boards.h" #include "hw/qdev-properties.h" #include "qemu/error-report.h" @@ -84,6 +85,11 @@ static const TypeInfo imx6_machine_types[] = { .name = MACHINE_TYPE_NAME("mcimx6ul-evk"), .parent = TYPE_MACHINE, .class_init = mcimx6ul_evk_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/mcimx7d-sabre.c b/hw/arm/mcimx7d-sabre.c index f5dc9c211dd..b236a6587eb 100644 --- a/hw/arm/mcimx7d-sabre.c +++ b/hw/arm/mcimx7d-sabre.c @@ -16,6 +16,7 @@ #include "qapi/error.h" #include "hw/arm/fsl-imx7.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "hw/boards.h" #include "hw/qdev-properties.h" #include "qemu/error-report.h" @@ -84,6 +85,11 @@ static const TypeInfo imx7_machine_types[] = { .name = MACHINE_TYPE_NAME("mcimx7d-sabre"), .parent = TYPE_MACHINE, .class_init = mcimx7d_sabre_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c index ade363daaa4..d34b1c675e5 100644 --- a/hw/arm/microbit.c +++ b/hw/arm/microbit.c @@ -12,6 +12,7 @@ #include "qapi/error.h" #include "hw/boards.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "system/system.h" #include "system/address-spaces.h" @@ -74,6 +75,11 @@ static const TypeInfo microbit_info = { .parent = TYPE_MACHINE, .instance_size = sizeof(MicrobitMachineState), .class_init = microbit_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void microbit_machine_init(void) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index b0633a5a69e..12512477977 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -52,6 +52,7 @@ #include "qemu/error-report.h" #include "hw/arm/boot.h" #include "hw/arm/armv7m.h" +#include "hw/arm/machines-qom.h" #include "hw/or-irq.h" #include "hw/boards.h" #include "system/address-spaces.h" @@ -1463,24 +1464,44 @@ static const TypeInfo mps2tz_an505_info = { .name = TYPE_MPS2TZ_AN505_MACHINE, .parent = TYPE_MPS2TZ_MACHINE, .class_init = mps2tz_an505_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static const TypeInfo mps2tz_an521_info = { .name = TYPE_MPS2TZ_AN521_MACHINE, .parent = TYPE_MPS2TZ_MACHINE, .class_init = mps2tz_an521_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static const TypeInfo mps3tz_an524_info = { .name = TYPE_MPS3TZ_AN524_MACHINE, .parent = TYPE_MPS2TZ_MACHINE, .class_init = mps3tz_an524_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static const TypeInfo mps3tz_an547_info = { .name = TYPE_MPS3TZ_AN547_MACHINE, .parent = TYPE_MPS2TZ_MACHINE, .class_init = mps3tz_an547_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void mps2tz_machine_init(void) diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c index 6958485a668..f39176c0005 100644 --- a/hw/arm/mps2.c +++ b/hw/arm/mps2.c @@ -31,6 +31,7 @@ #include "qemu/error-report.h" #include "hw/arm/boot.h" #include "hw/arm/armv7m.h" +#include "hw/arm/machines-qom.h" #include "hw/or-irq.h" #include "hw/boards.h" #include "system/address-spaces.h" @@ -563,24 +564,44 @@ static const TypeInfo mps2_an385_info = { .name = TYPE_MPS2_AN385_MACHINE, .parent = TYPE_MPS2_MACHINE, .class_init = mps2_an385_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static const TypeInfo mps2_an386_info = { .name = TYPE_MPS2_AN386_MACHINE, .parent = TYPE_MPS2_MACHINE, .class_init = mps2_an386_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static const TypeInfo mps2_an500_info = { .name = TYPE_MPS2_AN500_MACHINE, .parent = TYPE_MPS2_MACHINE, .class_init = mps2_an500_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static const TypeInfo mps2_an511_info = { .name = TYPE_MPS2_AN511_MACHINE, .parent = TYPE_MPS2_MACHINE, .class_init = mps2_an511_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void mps2_machine_init(void) diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c index 4dd1e8a7180..8bcf5a4d69f 100644 --- a/hw/arm/mps3r.c +++ b/hw/arm/mps3r.c @@ -37,6 +37,7 @@ #include "hw/qdev-properties.h" #include "hw/arm/boot.h" #include "hw/arm/bsa.h" +#include "hw/arm/machines-qom.h" #include "hw/char/cmsdk-apb-uart.h" #include "hw/i2c/arm_sbcon_i2c.h" #include "hw/intc/arm_gicv3.h" @@ -634,6 +635,11 @@ static const TypeInfo mps3r_machine_types[] = { .name = TYPE_MPS3R_AN536_MACHINE, .parent = TYPE_MPS3R_MACHINE, .class_init = mps3r_an536_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c index 6ce47eaa27a..3f7aefc0ba4 100644 --- a/hw/arm/msf2-som.c +++ b/hw/arm/msf2-som.c @@ -32,6 +32,7 @@ #include "hw/boards.h" #include "hw/qdev-properties.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "hw/qdev-clock.h" #include "system/address-spaces.h" #include "hw/arm/msf2-soc.h" @@ -114,6 +115,11 @@ static const TypeInfo msf2_machine_types[] = { .name = MACHINE_TYPE_NAME("emcraft-sf2"), .parent = TYPE_MACHINE, .class_init = emcraft_sf2_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/musca.c b/hw/arm/musca.c index a4f43f1992b..608f16f69b2 100644 --- a/hw/arm/musca.c +++ b/hw/arm/musca.c @@ -26,6 +26,7 @@ #include "system/system.h" #include "hw/arm/boot.h" #include "hw/arm/armsse.h" +#include "hw/arm/machines-qom.h" #include "hw/boards.h" #include "hw/char/pl011.h" #include "hw/core/split-irq.h" @@ -657,12 +658,22 @@ static const TypeInfo musca_a_info = { .name = TYPE_MUSCA_A_MACHINE, .parent = TYPE_MUSCA_MACHINE, .class_init = musca_a_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static const TypeInfo musca_b1_info = { .name = TYPE_MUSCA_B1_MACHINE, .parent = TYPE_MUSCA_MACHINE, .class_init = musca_b1_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void musca_machine_init(void) diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c index f7c488cd1d6..e2a65f72095 100644 --- a/hw/arm/musicpal.c +++ b/hw/arm/musicpal.c @@ -15,6 +15,7 @@ #include "hw/sysbus.h" #include "migration/vmstate.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "net/net.h" #include "system/system.h" #include "hw/boards.h" @@ -1381,6 +1382,11 @@ static const TypeInfo musicpal_types[] = { .name = MACHINE_TYPE_NAME("musicpal"), .parent = TYPE_MACHINE, .class_init = musicpal_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c index 52c30055d44..2e615276902 100644 --- a/hw/arm/netduino2.c +++ b/hw/arm/netduino2.c @@ -30,6 +30,7 @@ #include "qemu/error-report.h" #include "hw/arm/stm32f205_soc.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" /* Main SYSCLK frequency in Hz (120MHz) */ #define SYSCLK_FRQ 120000000ULL @@ -71,6 +72,11 @@ static const TypeInfo netduino_machine_types[] = { .name = MACHINE_TYPE_NAME("netduino2"), .parent = TYPE_MACHINE, .class_init = netduino2_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c index 2735d3a0e2b..e12f78599c4 100644 --- a/hw/arm/netduinoplus2.c +++ b/hw/arm/netduinoplus2.c @@ -30,6 +30,7 @@ #include "qemu/error-report.h" #include "hw/arm/stm32f405_soc.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" /* Main SYSCLK frequency in Hz (168MHz) */ #define SYSCLK_FRQ 168000000ULL @@ -71,6 +72,11 @@ static const TypeInfo netduino_machine_types[] = { .name = MACHINE_TYPE_NAME("netduinoplus2"), .parent = TYPE_MACHINE, .class_init = netduinoplus2_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c index eb28b97ad83..4b6d3443d53 100644 --- a/hw/arm/npcm7xx_boards.c +++ b/hw/arm/npcm7xx_boards.c @@ -17,6 +17,7 @@ #include "qemu/osdep.h" #include "hw/arm/npcm7xx.h" +#include "hw/arm/machines-qom.h" #include "hw/core/cpu.h" #include "hw/i2c/i2c_mux_pca954x.h" #include "hw/i2c/smbus_eeprom.h" @@ -549,22 +550,47 @@ static const TypeInfo npcm7xx_machine_types[] = { .name = MACHINE_TYPE_NAME("npcm750-evb"), .parent = TYPE_NPCM7XX_MACHINE, .class_init = npcm750_evb_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("quanta-gsj"), .parent = TYPE_NPCM7XX_MACHINE, .class_init = gsj_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("quanta-gbs-bmc"), .parent = TYPE_NPCM7XX_MACHINE, .class_init = gbs_bmc_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("kudo-bmc"), .parent = TYPE_NPCM7XX_MACHINE, .class_init = kudo_bmc_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("mori-bmc"), .parent = TYPE_NPCM7XX_MACHINE, .class_init = mori_bmc_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/npcm8xx_boards.c b/hw/arm/npcm8xx_boards.c index 3fb8478e72e..919c14dd809 100644 --- a/hw/arm/npcm8xx_boards.c +++ b/hw/arm/npcm8xx_boards.c @@ -19,6 +19,7 @@ #include "chardev/char.h" #include "hw/boards.h" #include "hw/arm/npcm8xx.h" +#include "hw/arm/machines-qom.h" #include "hw/core/cpu.h" #include "hw/loader.h" #include "hw/qdev-core.h" @@ -248,6 +249,10 @@ static const TypeInfo npcm8xx_machine_types[] = { .name = MACHINE_TYPE_NAME("npcm845-evb"), .parent = TYPE_NPCM8XX_MACHINE, .class_init = npcm845_evb_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/olimex-stm32-h405.c b/hw/arm/olimex-stm32-h405.c index 795218c93cf..f81f4094149 100644 --- a/hw/arm/olimex-stm32-h405.c +++ b/hw/arm/olimex-stm32-h405.c @@ -31,6 +31,7 @@ #include "qemu/error-report.h" #include "hw/arm/stm32f405_soc.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" /* olimex-stm32-h405 implementation is derived from netduinoplus2 */ @@ -77,6 +78,11 @@ static const TypeInfo olimex_stm32_machine_types[] = { .name = MACHINE_TYPE_NAME("olimex-stm32-h405"), .parent = TYPE_MACHINE, .class_init = olimex_stm32_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c index aa1e96b3ad7..2537045c1ac 100644 --- a/hw/arm/omap_sx1.c +++ b/hw/arm/omap_sx1.c @@ -32,6 +32,7 @@ #include "hw/arm/omap.h" #include "hw/boards.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "hw/block/flash.h" #include "system/qtest.h" #include "system/address-spaces.h" @@ -219,6 +220,11 @@ static const TypeInfo sx1_machine_v2_type = { .name = MACHINE_TYPE_NAME("sx1"), .parent = TYPE_MACHINE, .class_init = sx1_machine_v2_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void sx1_machine_v1_class_init(ObjectClass *oc, void *data) @@ -238,6 +244,11 @@ static const TypeInfo sx1_machine_v1_type = { .name = MACHINE_TYPE_NAME("sx1-v1"), .parent = TYPE_MACHINE, .class_init = sx1_machine_v1_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void sx1_machine_init(void) diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c index 6821033bfd7..4e333d428a2 100644 --- a/hw/arm/orangepi.c +++ b/hw/arm/orangepi.c @@ -26,6 +26,7 @@ #include "hw/qdev-properties.h" #include "hw/arm/allwinner-h3.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" static struct arm_boot_info orangepi_binfo; @@ -130,6 +131,11 @@ static const TypeInfo orangepi_machine_types[] = { .name = MACHINE_TYPE_NAME("orangepi-pc"), .parent = TYPE_MACHINE, .class_init = orangepi_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index dce35ca11aa..69cccdbb6b1 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -25,6 +25,7 @@ #include "hw/boards.h" #include "hw/loader.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "qom/object.h" #define TYPE_RASPI_MACHINE MACHINE_TYPE_NAME("raspi-common") @@ -394,23 +395,46 @@ static const TypeInfo raspi_machine_types[] = { .name = MACHINE_TYPE_NAME("raspi0"), .parent = TYPE_RASPI_MACHINE, .class_init = raspi0_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("raspi1ap"), .parent = TYPE_RASPI_MACHINE, .class_init = raspi1ap_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("raspi2b"), .parent = TYPE_RASPI_MACHINE, .class_init = raspi2b_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, #ifdef TARGET_AARCH64 }, { .name = MACHINE_TYPE_NAME("raspi3ap"), .parent = TYPE_RASPI_MACHINE, .class_init = raspi3ap_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("raspi3b"), .parent = TYPE_RASPI_MACHINE, .class_init = raspi3b_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, #endif }, { .name = TYPE_RASPI_MACHINE, diff --git a/hw/arm/raspi4b.c b/hw/arm/raspi4b.c index f6de103a3e1..8fda6d3b0ca 100644 --- a/hw/arm/raspi4b.c +++ b/hw/arm/raspi4b.c @@ -11,6 +11,7 @@ #include "qemu/cutils.h" #include "qapi/error.h" #include "qapi/visitor.h" +#include "hw/arm/machines-qom.h" #include "hw/arm/raspi_platform.h" #include "hw/display/bcm2835_fb.h" #include "hw/registerfields.h" @@ -127,6 +128,10 @@ static const TypeInfo raspi4b_machine_type = { .parent = TYPE_RASPI_BASE_MACHINE, .instance_size = sizeof(Raspi4bMachineState), .class_init = raspi4b_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void raspi4b_machine_register_type(void) diff --git a/hw/arm/realview.c b/hw/arm/realview.c index 008eeaf049a..aed864bcd4f 100644 --- a/hw/arm/realview.c +++ b/hw/arm/realview.c @@ -13,6 +13,7 @@ #include "hw/sysbus.h" #include "hw/arm/boot.h" #include "hw/arm/primecell.h" +#include "hw/arm/machines-qom.h" #include "hw/core/split-irq.h" #include "hw/net/lan9118.h" #include "hw/net/smc91c111.h" @@ -431,6 +432,11 @@ static const TypeInfo realview_eb_type = { .name = MACHINE_TYPE_NAME("realview-eb"), .parent = TYPE_MACHINE, .class_init = realview_eb_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void realview_eb_mpcore_class_init(ObjectClass *oc, void *data) @@ -452,6 +458,11 @@ static const TypeInfo realview_eb_mpcore_type = { .name = MACHINE_TYPE_NAME("realview-eb-mpcore"), .parent = TYPE_MACHINE, .class_init = realview_eb_mpcore_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void realview_pb_a8_class_init(ObjectClass *oc, void *data) @@ -471,6 +482,11 @@ static const TypeInfo realview_pb_a8_type = { .name = MACHINE_TYPE_NAME("realview-pb-a8"), .parent = TYPE_MACHINE, .class_init = realview_pb_a8_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void realview_pbx_a9_class_init(ObjectClass *oc, void *data) @@ -491,6 +507,11 @@ static const TypeInfo realview_pbx_a9_type = { .name = MACHINE_TYPE_NAME("realview-pbx-a9"), .parent = TYPE_MACHINE, .class_init = realview_pbx_a9_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void realview_machine_init(void) diff --git a/hw/arm/sabrelite.c b/hw/arm/sabrelite.c index ea59ba301e7..bc472dcad2c 100644 --- a/hw/arm/sabrelite.c +++ b/hw/arm/sabrelite.c @@ -14,6 +14,7 @@ #include "qapi/error.h" #include "hw/arm/fsl-imx6.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "hw/boards.h" #include "hw/qdev-properties.h" #include "qemu/error-report.h" @@ -120,6 +121,11 @@ static const TypeInfo sabrelite_machine_types[] = { .name = MACHINE_TYPE_NAME("sabrelite"), .parent = TYPE_MACHINE, .class_init = sabrelite_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index aa09d7a0917..6584097fc25 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -34,6 +34,7 @@ #include "hw/arm/bsa.h" #include "hw/arm/fdt.h" #include "hw/arm/smmuv3.h" +#include "hw/arm/machines-qom.h" #include "hw/block/flash.h" #include "hw/boards.h" #include "hw/ide/ide-bus.h" @@ -920,6 +921,10 @@ static const TypeInfo sbsa_ref_info = { .instance_init = sbsa_ref_instance_init, .class_init = sbsa_ref_class_init, .instance_size = sizeof(SBSAMachineState), + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void sbsa_ref_machine_init(void) diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index cbe914c93e9..8dc68c145c1 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -15,6 +15,7 @@ #include "hw/sd/sd.h" #include "hw/ssi/ssi.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "qemu/timer.h" #include "hw/i2c/i2c.h" #include "net/net.h" @@ -1427,6 +1428,11 @@ static const TypeInfo lm3s811evb_type = { .name = MACHINE_TYPE_NAME("lm3s811evb"), .parent = TYPE_MACHINE, .class_init = lm3s811evb_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; /* @@ -1448,6 +1454,11 @@ static const TypeInfo lm3s6965evb_type = { .name = MACHINE_TYPE_NAME("lm3s6965evb"), .parent = TYPE_MACHINE, .class_init = lm3s6965evb_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void stellaris_machine_init(void) diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c index 3a9728ca719..b7eb948bc2d 100644 --- a/hw/arm/stm32vldiscovery.c +++ b/hw/arm/stm32vldiscovery.c @@ -31,6 +31,7 @@ #include "qemu/error-report.h" #include "hw/arm/stm32f100_soc.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" /* stm32vldiscovery implementation is derived from netduinoplus2 */ @@ -74,6 +75,11 @@ static const TypeInfo stm32vldiscovery_machine_types[] = { .name = MACHINE_TYPE_NAME("stm32vldiscovery"), .parent = TYPE_MACHINE, .class_init = stm32vldiscovery_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c index 35766445fa4..defc4d7d170 100644 --- a/hw/arm/versatilepb.c +++ b/hw/arm/versatilepb.c @@ -12,6 +12,7 @@ #include "hw/sysbus.h" #include "migration/vmstate.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "hw/net/smc91c111.h" #include "net/net.h" #include "system/system.h" @@ -431,6 +432,11 @@ static const TypeInfo versatilepb_type = { .name = MACHINE_TYPE_NAME("versatilepb"), .parent = TYPE_MACHINE, .class_init = versatilepb_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void versatileab_class_init(ObjectClass *oc, void *data) @@ -452,6 +458,11 @@ static const TypeInfo versatileab_type = { .name = MACHINE_TYPE_NAME("versatileab"), .parent = TYPE_MACHINE, .class_init = versatileab_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void versatile_machine_init(void) diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c index 76c6107766c..38b203b52da 100644 --- a/hw/arm/vexpress.c +++ b/hw/arm/vexpress.c @@ -27,6 +27,7 @@ #include "hw/sysbus.h" #include "hw/arm/boot.h" #include "hw/arm/primecell.h" +#include "hw/arm/machines-qom.h" #include "hw/net/lan9118.h" #include "hw/i2c/i2c.h" #include "net/net.h" @@ -850,6 +851,11 @@ static const TypeInfo vexpress_a9_info = { .parent = TYPE_VEXPRESS_MACHINE, .class_init = vexpress_a9_class_init, .instance_init = vexpress_a9_instance_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static const TypeInfo vexpress_a15_info = { @@ -857,6 +863,11 @@ static const TypeInfo vexpress_a15_info = { .parent = TYPE_VEXPRESS_MACHINE, .class_init = vexpress_a15_class_init, .instance_init = vexpress_a15_instance_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void vexpress_machine_init(void) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index a96452f17a4..a3c9ffe29eb 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -37,6 +37,7 @@ #include "hw/arm/boot.h" #include "hw/arm/primecell.h" #include "hw/arm/virt.h" +#include "hw/arm/machines-qom.h" #include "hw/block/flash.h" #include "hw/vfio/vfio-calxeda-xgmac.h" #include "hw/vfio/vfio-amd-xgbe.h" @@ -123,6 +124,11 @@ static void arm_virt_compat_set(MachineClass *mc) .name = MACHINE_VER_TYPE_NAME("virt", __VA_ARGS__), \ .parent = TYPE_VIRT_MACHINE, \ .class_init = MACHINE_VER_SYM(class_init, virt, __VA_ARGS__), \ + .interfaces = (InterfaceInfo[]) { \ + { TYPE_TARGET_ARM_MACHINE }, \ + { TYPE_TARGET_AARCH64_MACHINE }, \ + { }, \ + }, \ }; \ static void MACHINE_VER_SYM(register, virt, __VA_ARGS__)(void) \ { \ diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index b8916665ed6..433907093fa 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -20,6 +20,7 @@ #include "qapi/error.h" #include "hw/sysbus.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "net/net.h" #include "system/system.h" #include "hw/boards.h" @@ -480,6 +481,11 @@ static const TypeInfo zynq_machine_type = { .parent = TYPE_MACHINE, .class_init = zynq_machine_class_init, .instance_size = sizeof(ZynqMachineState), + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void zynq_machine_register_types(void) diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c index 0c6f0359e3d..cb7466f7250 100644 --- a/hw/arm/xlnx-versal-virt.c +++ b/hw/arm/xlnx-versal-virt.c @@ -20,6 +20,7 @@ #include "hw/qdev-properties.h" #include "hw/arm/xlnx-versal.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "target/arm/multiprocessing.h" #include "qom/object.h" @@ -833,6 +834,10 @@ static const TypeInfo versal_virt_machine_init_typeinfo = { .instance_init = versal_virt_machine_instance_init, .instance_size = sizeof(VersalVirt), .instance_finalize = versal_virt_machine_finalize, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void versal_virt_machine_init_register_types(void) diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c index 4fdb153e4d8..f730dbbd908 100644 --- a/hw/arm/xlnx-zcu102.c +++ b/hw/arm/xlnx-zcu102.c @@ -19,6 +19,7 @@ #include "qapi/error.h" #include "hw/arm/xlnx-zynqmp.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "hw/boards.h" #include "qemu/error-report.h" #include "qemu/log.h" @@ -303,6 +304,10 @@ static const TypeInfo xlnx_zcu102_machine_init_typeinfo = { .class_init = xlnx_zcu102_machine_class_init, .instance_init = xlnx_zcu102_machine_instance_init, .instance_size = sizeof(XlnxZCU102), + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void xlnx_zcu102_machine_init_register_types(void) -- 2.47.1 ^ permalink raw reply related [flat|nested] 66+ messages in thread
* Re: [RFC PATCH v4 06/19] hw/arm: Filter machine types for qemu-system-arm/aarch64 binaries 2025-04-22 14:54 ` [RFC PATCH v4 06/19] hw/arm: Filter machine types for qemu-system-arm/aarch64 binaries Philippe Mathieu-Daudé @ 2025-04-22 17:40 ` Richard Henderson 2025-04-23 16:34 ` Philippe Mathieu-Daudé 2025-04-23 17:07 ` Philippe Mathieu-Daudé 0 siblings, 2 replies; 66+ messages in thread From: Richard Henderson @ 2025-04-22 17:40 UTC (permalink / raw) To: Philippe Mathieu-Daudé, qemu-devel, Pierrick Bouvier; +Cc: Anton Johansson On 4/22/25 07:54, Philippe Mathieu-Daudé wrote: > Since the qemu-system-aarch64 binary is able to run > all machines indistinctly, simply register the > TYPE_TARGET_AARCH64_MACHINE interface for all > existing machines under the hw/arm/ directory. "indistinctly" is the wrong word. I'm not quite sure what you're trying to say in order to suggest a replacement. > diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c > index 82f42582fa3..ce4d49a9f59 100644 > --- a/hw/arm/aspeed.c > +++ b/hw/arm/aspeed.c > @@ -15,6 +15,7 @@ > #include "hw/arm/aspeed.h" > #include "hw/arm/aspeed_soc.h" > #include "hw/arm/aspeed_eeprom.h" > +#include "hw/arm/machines-qom.h" > #include "hw/block/flash.h" > #include "hw/i2c/i2c_mux_pca954x.h" > #include "hw/i2c/smbus_eeprom.h" > @@ -1760,91 +1761,199 @@ static const TypeInfo aspeed_machine_types[] = { > .name = MACHINE_TYPE_NAME("palmetto-bmc"), > .parent = TYPE_ASPEED_MACHINE, > .class_init = aspeed_machine_palmetto_class_init, > + .interfaces = (InterfaceInfo[]) { > + { TYPE_TARGET_ARM_MACHINE }, > + { TYPE_TARGET_AARCH64_MACHINE }, > + { }, > + }, > }, { > .name = MACHINE_TYPE_NAME("supermicrox11-bmc"), > .parent = TYPE_ASPEED_MACHINE, > .class_init = aspeed_machine_supermicrox11_bmc_class_init, > + .interfaces = (InterfaceInfo[]) { > + { TYPE_TARGET_ARM_MACHINE }, > + { TYPE_TARGET_AARCH64_MACHINE }, > + { }, > + }, Don't replicate these anonymous arrays. You want common extern InterfaceInfo arm_aarch64_machine_interfaces[]; extern InterfaceInfo aarch64_machine_interfaces[]; to be shared by all. As a cleanup, we really should make all of these const. r~ ^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [RFC PATCH v4 06/19] hw/arm: Filter machine types for qemu-system-arm/aarch64 binaries 2025-04-22 17:40 ` Richard Henderson @ 2025-04-23 16:34 ` Philippe Mathieu-Daudé 2025-04-23 17:43 ` Pierrick Bouvier 2025-04-23 17:07 ` Philippe Mathieu-Daudé 1 sibling, 1 reply; 66+ messages in thread From: Philippe Mathieu-Daudé @ 2025-04-23 16:34 UTC (permalink / raw) To: Richard Henderson, qemu-devel, Pierrick Bouvier; +Cc: Anton Johansson On 22/4/25 19:40, Richard Henderson wrote: > On 4/22/25 07:54, Philippe Mathieu-Daudé wrote: >> Since the qemu-system-aarch64 binary is able to run >> all machines indistinctly, simply register the >> TYPE_TARGET_AARCH64_MACHINE interface for all >> existing machines under the hw/arm/ directory. > > "indistinctly" is the wrong word. I'm not quite sure what you're trying > to say in order to suggest a replacement. I want to express that qemu-system-aarch64 is a superset of qemu-system-arm machines. > >> diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c >> index 82f42582fa3..ce4d49a9f59 100644 >> --- a/hw/arm/aspeed.c >> +++ b/hw/arm/aspeed.c >> @@ -15,6 +15,7 @@ >> #include "hw/arm/aspeed.h" >> #include "hw/arm/aspeed_soc.h" >> #include "hw/arm/aspeed_eeprom.h" >> +#include "hw/arm/machines-qom.h" >> #include "hw/block/flash.h" >> #include "hw/i2c/i2c_mux_pca954x.h" >> #include "hw/i2c/smbus_eeprom.h" >> @@ -1760,91 +1761,199 @@ static const TypeInfo aspeed_machine_types[] = { >> .name = MACHINE_TYPE_NAME("palmetto-bmc"), >> .parent = TYPE_ASPEED_MACHINE, >> .class_init = aspeed_machine_palmetto_class_init, >> + .interfaces = (InterfaceInfo[]) { >> + { TYPE_TARGET_ARM_MACHINE }, >> + { TYPE_TARGET_AARCH64_MACHINE }, >> + { }, >> + }, >> }, { >> .name = MACHINE_TYPE_NAME("supermicrox11-bmc"), >> .parent = TYPE_ASPEED_MACHINE, >> .class_init = aspeed_machine_supermicrox11_bmc_class_init, >> + .interfaces = (InterfaceInfo[]) { >> + { TYPE_TARGET_ARM_MACHINE }, >> + { TYPE_TARGET_AARCH64_MACHINE }, >> + { }, >> + }, > > Don't replicate these anonymous arrays. > You want common > > extern InterfaceInfo arm_aarch64_machine_interfaces[]; > extern InterfaceInfo aarch64_machine_interfaces[]; > > to be shared by all. "common" was my first approach (not via extern but macro) https://lore.kernel.org/qemu-devel/20250403235821.9909-5-philmd@linaro.org/ but Pierrick said on offlist review we want this array to be verbose. Pierrick, are you OK with external symbols? ^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [RFC PATCH v4 06/19] hw/arm: Filter machine types for qemu-system-arm/aarch64 binaries 2025-04-23 16:34 ` Philippe Mathieu-Daudé @ 2025-04-23 17:43 ` Pierrick Bouvier 2025-04-23 19:12 ` Richard Henderson 0 siblings, 1 reply; 66+ messages in thread From: Pierrick Bouvier @ 2025-04-23 17:43 UTC (permalink / raw) To: Philippe Mathieu-Daudé, Richard Henderson, qemu-devel Cc: Anton Johansson On 4/23/25 09:34, Philippe Mathieu-Daudé wrote: > On 22/4/25 19:40, Richard Henderson wrote: >> On 4/22/25 07:54, Philippe Mathieu-Daudé wrote: >>> Since the qemu-system-aarch64 binary is able to run >>> all machines indistinctly, simply register the >>> TYPE_TARGET_AARCH64_MACHINE interface for all >>> existing machines under the hw/arm/ directory. >> >> "indistinctly" is the wrong word. I'm not quite sure what you're trying >> to say in order to suggest a replacement. > > I want to express that qemu-system-aarch64 is a superset of > qemu-system-arm machines. > >> >>> diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c >>> index 82f42582fa3..ce4d49a9f59 100644 >>> --- a/hw/arm/aspeed.c >>> +++ b/hw/arm/aspeed.c >>> @@ -15,6 +15,7 @@ >>> #include "hw/arm/aspeed.h" >>> #include "hw/arm/aspeed_soc.h" >>> #include "hw/arm/aspeed_eeprom.h" >>> +#include "hw/arm/machines-qom.h" >>> #include "hw/block/flash.h" >>> #include "hw/i2c/i2c_mux_pca954x.h" >>> #include "hw/i2c/smbus_eeprom.h" >>> @@ -1760,91 +1761,199 @@ static const TypeInfo aspeed_machine_types[] = { >>> .name = MACHINE_TYPE_NAME("palmetto-bmc"), >>> .parent = TYPE_ASPEED_MACHINE, >>> .class_init = aspeed_machine_palmetto_class_init, >>> + .interfaces = (InterfaceInfo[]) { >>> + { TYPE_TARGET_ARM_MACHINE }, >>> + { TYPE_TARGET_AARCH64_MACHINE }, >>> + { }, >>> + }, >>> }, { >>> .name = MACHINE_TYPE_NAME("supermicrox11-bmc"), >>> .parent = TYPE_ASPEED_MACHINE, >>> .class_init = aspeed_machine_supermicrox11_bmc_class_init, >>> + .interfaces = (InterfaceInfo[]) { >>> + { TYPE_TARGET_ARM_MACHINE }, >>> + { TYPE_TARGET_AARCH64_MACHINE }, >>> + { }, >>> + }, >> >> Don't replicate these anonymous arrays. >> You want common >> >> extern InterfaceInfo arm_aarch64_machine_interfaces[]; >> extern InterfaceInfo aarch64_machine_interfaces[]; >> >> to be shared by all. > @Richard: Is it a concern regarding code maintenance, or potential impact on .data? IMHO, it's worth repeating here, so it's easy to find all occurrences in the codebase. > "common" was my first approach (not via extern but macro) > https://lore.kernel.org/qemu-devel/20250403235821.9909-5-philmd@linaro.org/ > but Pierrick said on offlist review we want this array to > be verbose. > > Pierrick, are you OK with external symbols? > I'm not opposed to it, as long as we make it consistent through all our boards, and all architectures, whether they are defined with the full struct, or using any macro. The last thing we want is to have to do multiple greps to find information. The advantage of explicitly listing this is that it's unambiguous and easy to find. If the Richard's concern is just for code writing, maybe we can add a variadic macro to reduce boilerplate to a minimum, so we can have: .interfaces = TARGET_MACHINE(ARM, AARCH64). or DEFINE_MACHINE(..., TARGET_MACHINE(ARM, AARCH64)) ^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [RFC PATCH v4 06/19] hw/arm: Filter machine types for qemu-system-arm/aarch64 binaries 2025-04-23 17:43 ` Pierrick Bouvier @ 2025-04-23 19:12 ` Richard Henderson 2025-04-23 19:33 ` Pierrick Bouvier 0 siblings, 1 reply; 66+ messages in thread From: Richard Henderson @ 2025-04-23 19:12 UTC (permalink / raw) To: Pierrick Bouvier, Philippe Mathieu-Daudé, qemu-devel; +Cc: Anton Johansson On 4/23/25 10:43, Pierrick Bouvier wrote: >>>> + .interfaces = (InterfaceInfo[]) { >>>> + { TYPE_TARGET_ARM_MACHINE }, >>>> + { TYPE_TARGET_AARCH64_MACHINE }, >>>> + { }, >>>> + }, >>> >>> Don't replicate these anonymous arrays. >>> You want common >>> >>> extern InterfaceInfo arm_aarch64_machine_interfaces[]; >>> extern InterfaceInfo aarch64_machine_interfaces[]; >>> >>> to be shared by all. >> > > @Richard: > Is it a concern regarding code maintenance, or potential impact on .data? I was thinking of impact on .data, especially with so many. r~ ^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [RFC PATCH v4 06/19] hw/arm: Filter machine types for qemu-system-arm/aarch64 binaries 2025-04-23 19:12 ` Richard Henderson @ 2025-04-23 19:33 ` Pierrick Bouvier 2025-04-23 19:53 ` Philippe Mathieu-Daudé 2025-04-23 20:04 ` Richard Henderson 0 siblings, 2 replies; 66+ messages in thread From: Pierrick Bouvier @ 2025-04-23 19:33 UTC (permalink / raw) To: Richard Henderson, Philippe Mathieu-Daudé, qemu-devel Cc: Anton Johansson On 4/23/25 12:12, Richard Henderson wrote: >> @Richard: >> Is it a concern regarding code maintenance, or potential impact on .data? > > I was thinking of impact on .data, especially with so many. > du qemu-system-aarch64 optimized and stripped (in kB): 31880 upstream 31896 upstream + this series So we have +16kB which is a size increase of +0.0005%. Even if we project something similar on other architectures (let's say x10), the final impact on binary size should be < 0.005%. Maybe it's a reasonable impact considering the trade off on coherency and readability through the codebase? Else, in case we make this array const, can we expect the linker to deduplicate it? I'm not familiar with how final .data section is assembled. ^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [RFC PATCH v4 06/19] hw/arm: Filter machine types for qemu-system-arm/aarch64 binaries 2025-04-23 19:33 ` Pierrick Bouvier @ 2025-04-23 19:53 ` Philippe Mathieu-Daudé 2025-04-23 20:10 ` Pierrick Bouvier 2025-04-23 20:04 ` Richard Henderson 1 sibling, 1 reply; 66+ messages in thread From: Philippe Mathieu-Daudé @ 2025-04-23 19:53 UTC (permalink / raw) To: Pierrick Bouvier, Richard Henderson, qemu-devel; +Cc: Anton Johansson On 23/4/25 21:33, Pierrick Bouvier wrote: > On 4/23/25 12:12, Richard Henderson wrote: >>> @Richard: >>> Is it a concern regarding code maintenance, or potential impact >>> on .data? >> >> I was thinking of impact on .data, especially with so many. >> > > du qemu-system-aarch64 optimized and stripped (in kB): > 31880 upstream > 31896 upstream + this series FYI same tag as a branch with InterfaceInfo constified: https://gitlab.com/philmd/qemu/-/tree/single-binary-hw-arm-rfc-v4-const > So we have +16kB which is a size increase of +0.0005%. > Even if we project something similar on other architectures (let's say > x10), the final impact on binary size should be < 0.005%. > > Maybe it's a reasonable impact considering the trade off on coherency > and readability through the codebase? > Else, in case we make this array const, can we expect the linker to > deduplicate it? I'm not familiar with how final .data section is assembled. ^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [RFC PATCH v4 06/19] hw/arm: Filter machine types for qemu-system-arm/aarch64 binaries 2025-04-23 19:53 ` Philippe Mathieu-Daudé @ 2025-04-23 20:10 ` Pierrick Bouvier 0 siblings, 0 replies; 66+ messages in thread From: Pierrick Bouvier @ 2025-04-23 20:10 UTC (permalink / raw) To: Philippe Mathieu-Daudé, Richard Henderson, qemu-devel Cc: Anton Johansson On 4/23/25 12:53, Philippe Mathieu-Daudé wrote: > On 23/4/25 21:33, Pierrick Bouvier wrote: >> On 4/23/25 12:12, Richard Henderson wrote: >>>> @Richard: >>>> Is it a concern regarding code maintenance, or potential impact >>>> on .data? >>> >>> I was thinking of impact on .data, especially with so many. >>> >> >> du qemu-system-aarch64 optimized and stripped (in kB): >> 31880 upstream >> 31896 upstream + this series > > FYI same tag as a branch with InterfaceInfo constified: > https://gitlab.com/philmd/qemu/-/tree/single-binary-hw-arm-rfc-v4-const > Maybe I missed something, but machine interfaces are not const on this branch. >> So we have +16kB which is a size increase of +0.0005%. >> Even if we project something similar on other architectures (let's say >> x10), the final impact on binary size should be < 0.005%. >> >> Maybe it's a reasonable impact considering the trade off on coherency >> and readability through the codebase? >> Else, in case we make this array const, can we expect the linker to >> deduplicate it? I'm not familiar with how final .data section is assembled. > ^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [RFC PATCH v4 06/19] hw/arm: Filter machine types for qemu-system-arm/aarch64 binaries 2025-04-23 19:33 ` Pierrick Bouvier 2025-04-23 19:53 ` Philippe Mathieu-Daudé @ 2025-04-23 20:04 ` Richard Henderson 2025-04-23 20:12 ` Pierrick Bouvier 1 sibling, 1 reply; 66+ messages in thread From: Richard Henderson @ 2025-04-23 20:04 UTC (permalink / raw) To: Pierrick Bouvier, Philippe Mathieu-Daudé, qemu-devel; +Cc: Anton Johansson On 4/23/25 12:33, Pierrick Bouvier wrote: > Else, in case we make this array const, can we expect the linker to deduplicate it? I'm > not familiar with how final .data section is assembled. No, we do not expect de-duplication. It's a "that would technically break the object model" thing. Const or not, static S *a = &(S){ }; static S *b = &(S){ }; assert(a != b); r~ ^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [RFC PATCH v4 06/19] hw/arm: Filter machine types for qemu-system-arm/aarch64 binaries 2025-04-23 20:04 ` Richard Henderson @ 2025-04-23 20:12 ` Pierrick Bouvier 0 siblings, 0 replies; 66+ messages in thread From: Pierrick Bouvier @ 2025-04-23 20:12 UTC (permalink / raw) To: Richard Henderson, Philippe Mathieu-Daudé, qemu-devel Cc: Anton Johansson On 4/23/25 13:04, Richard Henderson wrote: > On 4/23/25 12:33, Pierrick Bouvier wrote: >> Else, in case we make this array const, can we expect the linker to deduplicate it? I'm >> not familiar with how final .data section is assembled. > > No, we do not expect de-duplication. > It's a "that would technically break the object model" thing. > Const or not, > > static S *a = &(S){ }; > static S *b = &(S){ }; > assert(a != b); > I see. However, it's only type names, and not really object models (we don't duplicate interfaces themselves, but list of interfaces). Or did I miss something in QOM? > > r~ ^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [RFC PATCH v4 06/19] hw/arm: Filter machine types for qemu-system-arm/aarch64 binaries 2025-04-22 17:40 ` Richard Henderson 2025-04-23 16:34 ` Philippe Mathieu-Daudé @ 2025-04-23 17:07 ` Philippe Mathieu-Daudé 1 sibling, 0 replies; 66+ messages in thread From: Philippe Mathieu-Daudé @ 2025-04-23 17:07 UTC (permalink / raw) To: Richard Henderson, qemu-devel, Pierrick Bouvier; +Cc: Anton Johansson On 22/4/25 19:40, Richard Henderson wrote: > On 4/22/25 07:54, Philippe Mathieu-Daudé wrote: > extern InterfaceInfo arm_aarch64_machine_interfaces[]; > extern InterfaceInfo aarch64_machine_interfaces[]; > As a cleanup, we really should make all of these const. I'll see if I can rebase on top of https://lore.kernel.org/qemu-devel/20250212213249.45574-12-philmd@linaro.org/ ^ permalink raw reply [flat|nested] 66+ messages in thread
* [RFC PATCH v4 07/19] meson: Prepare to accept per-binary TargetInfo structure implementation 2025-04-22 14:54 [RFC PATCH v4 00/19] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé ` (5 preceding siblings ...) 2025-04-22 14:54 ` [RFC PATCH v4 06/19] hw/arm: Filter machine types for qemu-system-arm/aarch64 binaries Philippe Mathieu-Daudé @ 2025-04-22 14:54 ` Philippe Mathieu-Daudé 2025-04-22 17:41 ` Richard Henderson 2025-04-22 14:54 ` [RFC PATCH v4 08/19] config/target: Implement per-binary TargetInfo structure (ARM, AARCH64) Philippe Mathieu-Daudé ` (11 subsequent siblings) 18 siblings, 1 reply; 66+ messages in thread From: Philippe Mathieu-Daudé @ 2025-04-22 14:54 UTC (permalink / raw) To: qemu-devel, Pierrick Bouvier; +Cc: Richard Henderson, Anton Johansson If a file defining the binary TargetInfo structure is available, link with it. Otherwise keep using the stub. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- meson.build | 9 ++++++++- configs/targets/meson.build | 3 +++ 2 files changed, 11 insertions(+), 1 deletion(-) create mode 100644 configs/targets/meson.build diff --git a/meson.build b/meson.build index a1109b6db3f..69f60755377 100644 --- a/meson.build +++ b/meson.build @@ -3216,6 +3216,7 @@ config_devices_mak_list = [] config_devices_h = {} config_target_h = {} config_target_mak = {} +config_target_info = {} disassemblers = { 'alpha' : ['CONFIG_ALPHA_DIS'], @@ -3809,9 +3810,9 @@ specific_ss.add(files('page-target.c', 'page-vary-target.c')) common_ss.add(files('target-info.c')) system_ss.add(files('target-info-qom.c')) -specific_ss.add(files('target-info-stub.c')) subdir('backends') +subdir('configs/targets') subdir('disas') subdir('migration') subdir('monitor') @@ -4272,6 +4273,12 @@ foreach target : target_dirs arch_srcs += gdbstub_xml endif + if target in config_target_info + arch_srcs += config_target_info[target] + else + arch_srcs += files('target-info-stub.c') + endif + t = target_arch[target_base_arch].apply(config_target, strict: false) arch_srcs += t.sources() arch_deps += t.dependencies() diff --git a/configs/targets/meson.build b/configs/targets/meson.build new file mode 100644 index 00000000000..e9a5f7b078e --- /dev/null +++ b/configs/targets/meson.build @@ -0,0 +1,3 @@ +foreach target : ['arm-softmmu', 'aarch64-softmmu'] + config_target_info += {target : files(target + '.c')} +endforeach -- 2.47.1 ^ permalink raw reply related [flat|nested] 66+ messages in thread
* Re: [RFC PATCH v4 07/19] meson: Prepare to accept per-binary TargetInfo structure implementation 2025-04-22 14:54 ` [RFC PATCH v4 07/19] meson: Prepare to accept per-binary TargetInfo structure implementation Philippe Mathieu-Daudé @ 2025-04-22 17:41 ` Richard Henderson 0 siblings, 0 replies; 66+ messages in thread From: Richard Henderson @ 2025-04-22 17:41 UTC (permalink / raw) To: Philippe Mathieu-Daudé, qemu-devel, Pierrick Bouvier; +Cc: Anton Johansson On 4/22/25 07:54, Philippe Mathieu-Daudé wrote: > If a file defining the binary TargetInfo structure is available, > link with it. Otherwise keep using the stub. > > Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org> > Reviewed-by: Pierrick Bouvier<pierrick.bouvier@linaro.org> > --- > meson.build | 9 ++++++++- > configs/targets/meson.build | 3 +++ > 2 files changed, 11 insertions(+), 1 deletion(-) > create mode 100644 configs/targets/meson.build Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~ ^ permalink raw reply [flat|nested] 66+ messages in thread
* [RFC PATCH v4 08/19] config/target: Implement per-binary TargetInfo structure (ARM, AARCH64) 2025-04-22 14:54 [RFC PATCH v4 00/19] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé ` (6 preceding siblings ...) 2025-04-22 14:54 ` [RFC PATCH v4 07/19] meson: Prepare to accept per-binary TargetInfo structure implementation Philippe Mathieu-Daudé @ 2025-04-22 14:54 ` Philippe Mathieu-Daudé 2025-04-22 17:42 ` Richard Henderson 2025-04-22 14:54 ` [RFC PATCH v4 09/19] hw/arm/aspeed: Build objects once Philippe Mathieu-Daudé ` (10 subsequent siblings) 18 siblings, 1 reply; 66+ messages in thread From: Philippe Mathieu-Daudé @ 2025-04-22 14:54 UTC (permalink / raw) To: qemu-devel, Pierrick Bouvier; +Cc: Richard Henderson, Anton Johansson Implement the TargetInfo structure for qemu-system-arm and qemu-system-aarch64 binaries. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- MAINTAINERS | 1 + configs/targets/aarch64-softmmu.c | 22 ++++++++++++++++++++++ configs/targets/arm-softmmu.c | 22 ++++++++++++++++++++++ 3 files changed, 45 insertions(+) create mode 100644 configs/targets/aarch64-softmmu.c create mode 100644 configs/targets/arm-softmmu.c diff --git a/MAINTAINERS b/MAINTAINERS index a055f67b5fc..4edd1ba696a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1919,6 +1919,7 @@ M: Philippe Mathieu-Daudé <philmd@linaro.org> S: Supported F: include/qemu/target-info*.h F: target-info*.c +F: configs/targets/*.c Xtensa Machines --------------- diff --git a/configs/targets/aarch64-softmmu.c b/configs/targets/aarch64-softmmu.c new file mode 100644 index 00000000000..375e6fa0b7b --- /dev/null +++ b/configs/targets/aarch64-softmmu.c @@ -0,0 +1,22 @@ +/* + * QEMU binary/target API (qemu-system-aarch64) + * + * Copyright (c) Linaro + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/target-info-impl.h" +#include "hw/arm/machines-qom.h" +#include "target/arm/cpu-qom.h" + +static const TargetInfo target_info_aarch64_system = { + .target_name = "aarch64", + .machine_typename = TYPE_TARGET_AARCH64_MACHINE, +}; + +const TargetInfo *target_info(void) +{ + return &target_info_aarch64_system; +} diff --git a/configs/targets/arm-softmmu.c b/configs/targets/arm-softmmu.c new file mode 100644 index 00000000000..d4acdae64f3 --- /dev/null +++ b/configs/targets/arm-softmmu.c @@ -0,0 +1,22 @@ +/* + * QEMU binary/target API (qemu-system-arm) + * + * Copyright (c) Linaro + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/target-info-impl.h" +#include "hw/arm/machines-qom.h" +#include "target/arm/cpu-qom.h" + +static const TargetInfo target_info_arm_system = { + .target_name = "arm", + .machine_typename = TYPE_TARGET_ARM_MACHINE, +}; + +const TargetInfo *target_info(void) +{ + return &target_info_arm_system; +} -- 2.47.1 ^ permalink raw reply related [flat|nested] 66+ messages in thread
* Re: [RFC PATCH v4 08/19] config/target: Implement per-binary TargetInfo structure (ARM, AARCH64) 2025-04-22 14:54 ` [RFC PATCH v4 08/19] config/target: Implement per-binary TargetInfo structure (ARM, AARCH64) Philippe Mathieu-Daudé @ 2025-04-22 17:42 ` Richard Henderson 0 siblings, 0 replies; 66+ messages in thread From: Richard Henderson @ 2025-04-22 17:42 UTC (permalink / raw) To: Philippe Mathieu-Daudé, qemu-devel, Pierrick Bouvier; +Cc: Anton Johansson On 4/22/25 07:54, Philippe Mathieu-Daudé wrote: > Implement the TargetInfo structure for qemu-system-arm > and qemu-system-aarch64 binaries. > > Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org> > Reviewed-by: Pierrick Bouvier<pierrick.bouvier@linaro.org> > --- > MAINTAINERS | 1 + > configs/targets/aarch64-softmmu.c | 22 ++++++++++++++++++++++ > configs/targets/arm-softmmu.c | 22 ++++++++++++++++++++++ > 3 files changed, 45 insertions(+) > create mode 100644 configs/targets/aarch64-softmmu.c > create mode 100644 configs/targets/arm-softmmu.c Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~ ^ permalink raw reply [flat|nested] 66+ messages in thread
* [RFC PATCH v4 09/19] hw/arm/aspeed: Build objects once 2025-04-22 14:54 [RFC PATCH v4 00/19] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé ` (7 preceding siblings ...) 2025-04-22 14:54 ` [RFC PATCH v4 08/19] config/target: Implement per-binary TargetInfo structure (ARM, AARCH64) Philippe Mathieu-Daudé @ 2025-04-22 14:54 ` Philippe Mathieu-Daudé 2025-04-22 17:42 ` Richard Henderson 2025-04-22 14:54 ` [RFC PATCH v4 10/19] hw/arm/raspi: " Philippe Mathieu-Daudé ` (9 subsequent siblings) 18 siblings, 1 reply; 66+ messages in thread From: Philippe Mathieu-Daudé @ 2025-04-22 14:54 UTC (permalink / raw) To: qemu-devel, Pierrick Bouvier; +Cc: Richard Henderson, Anton Johansson Now than Aspeed machines can be filtered when running a qemu-system-arm or qemu-system-aarch64 binary, we can remove the TARGET_AARCH64 #ifdef'ry and compile the aspeed.c file once, moving it from arm_ss[] source set to arm_common_ss[]. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- hw/arm/aspeed.c | 6 ------ hw/arm/meson.build | 4 ++-- 2 files changed, 2 insertions(+), 8 deletions(-) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index ce4d49a9f59..6de61505a09 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -180,13 +180,11 @@ struct AspeedMachineState { #define AST2600_EVB_HW_STRAP1 0x000000C0 #define AST2600_EVB_HW_STRAP2 0x00000003 -#ifdef TARGET_AARCH64 /* AST2700 evb hardware value */ /* SCU HW Strap1 */ #define AST2700_EVB_HW_STRAP1 0x00000800 /* SCUIO HW Strap1 */ #define AST2700_EVB_HW_STRAP2 0x00000700 -#endif /* Rainier hardware value: (QEMU prototype) */ #define RAINIER_BMC_HW_STRAP1 (0x00422016 | SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC) @@ -1664,7 +1662,6 @@ static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc, aspeed_machine_class_init_cpus_defaults(mc); } -#ifdef TARGET_AARCH64 static void ast2700_evb_i2c_init(AspeedMachineState *bmc) { AspeedSoCState *soc = bmc->soc; @@ -1714,7 +1711,6 @@ static void aspeed_machine_ast2700a1_evb_class_init(ObjectClass *oc, void *data) mc->default_ram_size = 1 * GiB; aspeed_machine_class_init_cpus_defaults(mc); } -#endif static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc, void *data) @@ -1937,7 +1933,6 @@ static const TypeInfo aspeed_machine_types[] = { { TYPE_TARGET_AARCH64_MACHINE }, { }, }, -#ifdef TARGET_AARCH64 }, { .name = MACHINE_TYPE_NAME("ast2700a0-evb"), .parent = TYPE_ASPEED_MACHINE, @@ -1954,7 +1949,6 @@ static const TypeInfo aspeed_machine_types[] = { { TYPE_TARGET_AARCH64_MACHINE }, { }, }, -#endif }, { .name = TYPE_ASPEED_MACHINE, .parent = TYPE_MACHINE, diff --git a/hw/arm/meson.build b/hw/arm/meson.build index 09b1cfe5b57..f76e7fb229f 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -39,15 +39,15 @@ arm_common_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal.c', 'x arm_common_ss.add(when: 'CONFIG_FSL_IMX25', if_true: files('fsl-imx25.c', 'imx25_pdk.c')) arm_common_ss.add(when: 'CONFIG_FSL_IMX31', if_true: files('fsl-imx31.c', 'kzm.c')) arm_common_ss.add(when: 'CONFIG_FSL_IMX6', if_true: files('fsl-imx6.c')) -arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( +arm_common_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( 'aspeed.c', 'aspeed_soc_common.c', 'aspeed_ast2400.c', 'aspeed_ast2600.c', 'aspeed_ast10x0.c', + 'aspeed_ast27x0.c', 'aspeed_eeprom.c', 'fby35.c')) -arm_common_ss.add(when: ['CONFIG_ASPEED_SOC', 'TARGET_AARCH64'], if_true: files('aspeed_ast27x0.c')) arm_common_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2.c')) arm_common_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2-tz.c')) arm_common_ss.add(when: 'CONFIG_MSF2', if_true: files('msf2-soc.c')) -- 2.47.1 ^ permalink raw reply related [flat|nested] 66+ messages in thread
* Re: [RFC PATCH v4 09/19] hw/arm/aspeed: Build objects once 2025-04-22 14:54 ` [RFC PATCH v4 09/19] hw/arm/aspeed: Build objects once Philippe Mathieu-Daudé @ 2025-04-22 17:42 ` Richard Henderson 0 siblings, 0 replies; 66+ messages in thread From: Richard Henderson @ 2025-04-22 17:42 UTC (permalink / raw) To: Philippe Mathieu-Daudé, qemu-devel, Pierrick Bouvier; +Cc: Anton Johansson On 4/22/25 07:54, Philippe Mathieu-Daudé wrote: > Now than Aspeed machines can be filtered when running a > qemu-system-arm or qemu-system-aarch64 binary, we can > remove the TARGET_AARCH64 #ifdef'ry and compile the > aspeed.c file once, moving it from arm_ss[] source set > to arm_common_ss[]. > > Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org> > Reviewed-by: Pierrick Bouvier<pierrick.bouvier@linaro.org> > --- > hw/arm/aspeed.c | 6 ------ > hw/arm/meson.build | 4 ++-- > 2 files changed, 2 insertions(+), 8 deletions(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~ ^ permalink raw reply [flat|nested] 66+ messages in thread
* [RFC PATCH v4 10/19] hw/arm/raspi: Build objects once 2025-04-22 14:54 [RFC PATCH v4 00/19] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé ` (8 preceding siblings ...) 2025-04-22 14:54 ` [RFC PATCH v4 09/19] hw/arm/aspeed: Build objects once Philippe Mathieu-Daudé @ 2025-04-22 14:54 ` Philippe Mathieu-Daudé 2025-04-22 17:43 ` Richard Henderson 2025-04-22 14:54 ` [RFC PATCH v4 11/19] hw/core/machine: Allow dynamic registration of valid CPU types Philippe Mathieu-Daudé ` (8 subsequent siblings) 18 siblings, 1 reply; 66+ messages in thread From: Philippe Mathieu-Daudé @ 2025-04-22 14:54 UTC (permalink / raw) To: qemu-devel, Pierrick Bouvier; +Cc: Richard Henderson, Anton Johansson Now than Raspi machines can be filtered when running a qemu-system-arm or qemu-system-aarch64 binary, we can remove the TARGET_AARCH64 #ifdef'ry and compile the aspeed.c file once, moving it from arm_ss[] source set to arm_common_ss[]. Note, we expose the TYPE_BCM2837 type to qemu-system-arm, but it is not user-creatable, so not an issue. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- hw/arm/bcm2836.c | 4 ---- hw/arm/raspi.c | 4 ---- hw/arm/meson.build | 8 ++++++-- 3 files changed, 6 insertions(+), 10 deletions(-) diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index f60489983ba..454ea2208d7 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -196,7 +196,6 @@ static void bcm2836_class_init(ObjectClass *oc, void *data) dc->realize = bcm2836_realize; }; -#ifdef TARGET_AARCH64 static void bcm2837_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); @@ -209,7 +208,6 @@ static void bcm2837_class_init(ObjectClass *oc, void *data) bc->clusterid = 0x0; dc->realize = bcm2836_realize; }; -#endif static const TypeInfo bcm283x_types[] = { { @@ -220,12 +218,10 @@ static const TypeInfo bcm283x_types[] = { .name = TYPE_BCM2836, .parent = TYPE_BCM283X, .class_init = bcm2836_class_init, -#ifdef TARGET_AARCH64 }, { .name = TYPE_BCM2837, .parent = TYPE_BCM283X, .class_init = bcm2837_class_init, -#endif }, { .name = TYPE_BCM283X, .parent = TYPE_BCM283X_BASE, diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index 69cccdbb6b1..641e231db61 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -368,7 +368,6 @@ static void raspi2b_machine_class_init(ObjectClass *oc, void *data) raspi_machine_class_init(mc, rmc->board_rev); }; -#ifdef TARGET_AARCH64 static void raspi3ap_machine_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); @@ -388,7 +387,6 @@ static void raspi3b_machine_class_init(ObjectClass *oc, void *data) rmc->board_rev = 0xa02082; raspi_machine_class_init(mc, rmc->board_rev); }; -#endif /* TARGET_AARCH64 */ static const TypeInfo raspi_machine_types[] = { { @@ -418,7 +416,6 @@ static const TypeInfo raspi_machine_types[] = { { TYPE_TARGET_AARCH64_MACHINE }, { }, }, -#ifdef TARGET_AARCH64 }, { .name = MACHINE_TYPE_NAME("raspi3ap"), .parent = TYPE_RASPI_MACHINE, @@ -435,7 +432,6 @@ static const TypeInfo raspi_machine_types[] = { { TYPE_TARGET_AARCH64_MACHINE }, { }, }, -#endif }, { .name = TYPE_RASPI_MACHINE, .parent = TYPE_RASPI_BASE_MACHINE, diff --git a/hw/arm/meson.build b/hw/arm/meson.build index f76e7fb229f..f52034ff6a2 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -27,8 +27,12 @@ arm_common_ss.add(when: 'CONFIG_OMAP', if_true: files('omap1.c')) arm_common_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-a10.c', 'cubieboard.c')) arm_common_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c', 'orangepi.c')) arm_common_ss.add(when: 'CONFIG_ALLWINNER_R40', if_true: files('allwinner-r40.c', 'bananapi_m2u.c')) -arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2836.c', 'raspi.c')) -arm_common_ss.add(when: ['CONFIG_RASPI', 'TARGET_AARCH64'], if_true: files('bcm2838.c', 'raspi4b.c')) +arm_common_ss.add(when: 'CONFIG_RASPI', if_true: files( + 'bcm2836.c', + 'bcm2838.c', + 'raspi.c', + 'raspi4b.c', +)) arm_common_ss.add(when: 'CONFIG_STM32F100_SOC', if_true: files('stm32f100_soc.c')) arm_common_ss.add(when: 'CONFIG_STM32F205_SOC', if_true: files('stm32f205_soc.c')) arm_common_ss.add(when: 'CONFIG_STM32F405_SOC', if_true: files('stm32f405_soc.c')) -- 2.47.1 ^ permalink raw reply related [flat|nested] 66+ messages in thread
* Re: [RFC PATCH v4 10/19] hw/arm/raspi: Build objects once 2025-04-22 14:54 ` [RFC PATCH v4 10/19] hw/arm/raspi: " Philippe Mathieu-Daudé @ 2025-04-22 17:43 ` Richard Henderson 0 siblings, 0 replies; 66+ messages in thread From: Richard Henderson @ 2025-04-22 17:43 UTC (permalink / raw) To: Philippe Mathieu-Daudé, qemu-devel, Pierrick Bouvier; +Cc: Anton Johansson On 4/22/25 07:54, Philippe Mathieu-Daudé wrote: > Now than Raspi machines can be filtered when running a > qemu-system-arm or qemu-system-aarch64 binary, we can > remove the TARGET_AARCH64 #ifdef'ry and compile the > aspeed.c file once, moving it from arm_ss[] source set > to arm_common_ss[]. Note, we expose the TYPE_BCM2837 > type to qemu-system-arm, but it is not user-creatable, > so not an issue. > > Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org> > Reviewed-by: Pierrick Bouvier<pierrick.bouvier@linaro.org> > --- > hw/arm/bcm2836.c | 4 ---- > hw/arm/raspi.c | 4 ---- > hw/arm/meson.build | 8 ++++++-- > 3 files changed, 6 insertions(+), 10 deletions(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~ ^ permalink raw reply [flat|nested] 66+ messages in thread
* [RFC PATCH v4 11/19] hw/core/machine: Allow dynamic registration of valid CPU types 2025-04-22 14:54 [RFC PATCH v4 00/19] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé ` (9 preceding siblings ...) 2025-04-22 14:54 ` [RFC PATCH v4 10/19] hw/arm/raspi: " Philippe Mathieu-Daudé @ 2025-04-22 14:54 ` Philippe Mathieu-Daudé 2025-04-22 17:54 ` Richard Henderson 2025-04-22 14:54 ` [RFC PATCH v4 12/19] hw/arm/virt: Register valid CPU types dynamically Philippe Mathieu-Daudé ` (7 subsequent siblings) 18 siblings, 1 reply; 66+ messages in thread From: Philippe Mathieu-Daudé @ 2025-04-22 14:54 UTC (permalink / raw) To: qemu-devel, Pierrick Bouvier; +Cc: Richard Henderson, Anton Johansson Add MachineClass::get_valid_cpu_types(), a helper that returns a dynamic list of CPU types. Since the helper takes a MachineState argument, we know the machine is created by the time we call it. Suggested-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- include/hw/boards.h | 4 ++++ hw/core/machine.c | 27 +++++++++++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/include/hw/boards.h b/include/hw/boards.h index 02f43ac5d4d..be0c0f04804 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -259,6 +259,9 @@ typedef struct { * @smbios_memory_device_size: * Default size of memory device, * SMBIOS 3.1.0 "7.18 Memory Device (Type 17)" + * @get_valid_cpu_types: + * Returns a list of valid CPU types for this board. May be NULL + * if not needed. */ struct MachineClass { /*< private >*/ @@ -306,6 +309,7 @@ struct MachineClass { bool ignore_memory_transaction_failures; int numa_mem_align_shift; const char * const *valid_cpu_types; + GSList *(*get_valid_cpu_types)(const MachineState *ms); strList *allowed_dynamic_sysbus_devices; bool auto_enable_numa_with_memhp; bool auto_enable_numa_with_memdev; diff --git a/hw/core/machine.c b/hw/core/machine.c index f52a4f2273b..8b40735ef98 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -1581,6 +1581,33 @@ static bool is_cpu_type_supported(const MachineState *machine, Error **errp) return false; } } + if (mc->get_valid_cpu_types) { + GSList *vct = mc->get_valid_cpu_types(machine); + bool valid = false; + unsigned count = 0; + GSList *l; + + for (l = vct; !valid && l != NULL; l = l->next) { + valid |= !!object_class_dynamic_cast(oc, l->data); + count++; + } + + if (!valid) { + g_autofree char *requested = cpu_model_from_type(machine->cpu_type); + vct = g_slist_reverse(vct); + error_setg(errp, "Invalid CPU model: %s", requested); + error_append_hint(errp, "The valid models are: "); + for (l = vct; l != NULL; l = l->next) { + g_autofree char *model = cpu_model_from_type(l->data); + error_append_hint(errp, "%s%s", model, --count ? ", " : ""); + } + error_append_hint(errp, "\n"); + } + g_slist_free_full(vct, g_free); + if (!valid) { + return false; + } + } /* Check if CPU type is deprecated and warn if so */ cc = CPU_CLASS(oc); -- 2.47.1 ^ permalink raw reply related [flat|nested] 66+ messages in thread
* Re: [RFC PATCH v4 11/19] hw/core/machine: Allow dynamic registration of valid CPU types 2025-04-22 14:54 ` [RFC PATCH v4 11/19] hw/core/machine: Allow dynamic registration of valid CPU types Philippe Mathieu-Daudé @ 2025-04-22 17:54 ` Richard Henderson 2025-04-22 18:06 ` Pierrick Bouvier 0 siblings, 1 reply; 66+ messages in thread From: Richard Henderson @ 2025-04-22 17:54 UTC (permalink / raw) To: Philippe Mathieu-Daudé, qemu-devel, Pierrick Bouvier; +Cc: Anton Johansson On 4/22/25 07:54, Philippe Mathieu-Daudé wrote: > index f52a4f2273b..8b40735ef98 100644 > --- a/hw/core/machine.c > +++ b/hw/core/machine.c > @@ -1581,6 +1581,33 @@ static bool is_cpu_type_supported(const MachineState *machine, Error **errp) > return false; > } > } > + if (mc->get_valid_cpu_types) { > + GSList *vct = mc->get_valid_cpu_types(machine); > + bool valid = false; > + unsigned count = 0; > + GSList *l; > + > + for (l = vct; !valid && l != NULL; l = l->next) { > + valid |= !!object_class_dynamic_cast(oc, l->data); > + count++; > + } > + > + if (!valid) { > + g_autofree char *requested = cpu_model_from_type(machine->cpu_type); > + vct = g_slist_reverse(vct); > + error_setg(errp, "Invalid CPU model: %s", requested); > + error_append_hint(errp, "The valid models are: "); > + for (l = vct; l != NULL; l = l->next) { > + g_autofree char *model = cpu_model_from_type(l->data); > + error_append_hint(errp, "%s%s", model, --count ? ", " : ""); > + } > + error_append_hint(errp, "\n"); > + } > + g_slist_free_full(vct, g_free); > + if (!valid) { > + return false; > + } > + } Why use GSList instead of GPtrArray? That would provide you the count without manually computing it, and it would avoid the need for any sort of reverse. I think it would also allow you to auto-free the set. r~ ^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [RFC PATCH v4 11/19] hw/core/machine: Allow dynamic registration of valid CPU types 2025-04-22 17:54 ` Richard Henderson @ 2025-04-22 18:06 ` Pierrick Bouvier 0 siblings, 0 replies; 66+ messages in thread From: Pierrick Bouvier @ 2025-04-22 18:06 UTC (permalink / raw) To: Richard Henderson, Philippe Mathieu-Daudé, qemu-devel Cc: Anton Johansson On 4/22/25 10:54, Richard Henderson wrote: > On 4/22/25 07:54, Philippe Mathieu-Daudé wrote: >> index f52a4f2273b..8b40735ef98 100644 >> --- a/hw/core/machine.c >> +++ b/hw/core/machine.c >> @@ -1581,6 +1581,33 @@ static bool is_cpu_type_supported(const MachineState *machine, Error **errp) >> return false; >> } >> } >> + if (mc->get_valid_cpu_types) { >> + GSList *vct = mc->get_valid_cpu_types(machine); >> + bool valid = false; >> + unsigned count = 0; >> + GSList *l; >> + >> + for (l = vct; !valid && l != NULL; l = l->next) { >> + valid |= !!object_class_dynamic_cast(oc, l->data); >> + count++; >> + } >> + >> + if (!valid) { >> + g_autofree char *requested = cpu_model_from_type(machine->cpu_type); >> + vct = g_slist_reverse(vct); >> + error_setg(errp, "Invalid CPU model: %s", requested); >> + error_append_hint(errp, "The valid models are: "); >> + for (l = vct; l != NULL; l = l->next) { >> + g_autofree char *model = cpu_model_from_type(l->data); >> + error_append_hint(errp, "%s%s", model, --count ? ", " : ""); >> + } >> + error_append_hint(errp, "\n"); >> + } >> + g_slist_free_full(vct, g_free); >> + if (!valid) { >> + return false; >> + } >> + } > > Why use GSList instead of GPtrArray? > That would provide you the count without manually computing it, > and it would avoid the need for any sort of reverse. > I think it would also allow you to auto-free the set. > Same remark than Richard, it would remove all the checks needed, as we can simply use this array "blindly". > > r~ ^ permalink raw reply [flat|nested] 66+ messages in thread
* [RFC PATCH v4 12/19] hw/arm/virt: Register valid CPU types dynamically 2025-04-22 14:54 [RFC PATCH v4 00/19] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé ` (10 preceding siblings ...) 2025-04-22 14:54 ` [RFC PATCH v4 11/19] hw/core/machine: Allow dynamic registration of valid CPU types Philippe Mathieu-Daudé @ 2025-04-22 14:54 ` Philippe Mathieu-Daudé 2025-04-22 17:56 ` Richard Henderson 2025-04-22 14:54 ` [RFC PATCH v4 13/19] hw/arm/virt: Check accelerator availability at runtime Philippe Mathieu-Daudé ` (6 subsequent siblings) 18 siblings, 1 reply; 66+ messages in thread From: Philippe Mathieu-Daudé @ 2025-04-22 14:54 UTC (permalink / raw) To: qemu-devel, Pierrick Bouvier; +Cc: Richard Henderson, Anton Johansson Replace the static array returned as MachineClass::valid_cpu_types[] by a runtime one generated by MachineClass::get_valid_cpu_types() once the machine is created (its options being processed). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- hw/arm/virt.c | 59 ++++++++++++++++++++++++++++----------------------- 1 file changed, 32 insertions(+), 27 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index a3c9ffe29eb..c6ae7cc1705 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -3130,36 +3130,41 @@ static int virt_hvf_get_physical_address_range(MachineState *ms) return requested_ipa_size; } +static GSList *virt_get_valid_cpu_types(const MachineState *ms) +{ + GSList *vct = NULL; + +#ifdef CONFIG_TCG + vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a7"))); + vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a15"))); +#ifdef TARGET_AARCH64 + vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a35"))); + vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a55"))); + vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a72"))); + vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a76"))); + vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a710"))); + vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("a64fx"))); + vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-n1"))); + vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-v1"))); + vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-n2"))); +#endif /* TARGET_AARCH64 */ +#endif /* CONFIG_TCG */ +#ifdef TARGET_AARCH64 + vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a53"))); + vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a57"))); +#if defined(CONFIG_KVM) || defined(CONFIG_HVF) + vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("host"))); +#endif /* CONFIG_KVM || CONFIG_HVF */ +#endif /* TARGET_AARCH64 */ + vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("max"))); + + return vct; +} + static void virt_machine_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); - static const char * const valid_cpu_types[] = { -#ifdef CONFIG_TCG - ARM_CPU_TYPE_NAME("cortex-a7"), - ARM_CPU_TYPE_NAME("cortex-a15"), -#ifdef TARGET_AARCH64 - ARM_CPU_TYPE_NAME("cortex-a35"), - ARM_CPU_TYPE_NAME("cortex-a55"), - ARM_CPU_TYPE_NAME("cortex-a72"), - ARM_CPU_TYPE_NAME("cortex-a76"), - ARM_CPU_TYPE_NAME("cortex-a710"), - ARM_CPU_TYPE_NAME("a64fx"), - ARM_CPU_TYPE_NAME("neoverse-n1"), - ARM_CPU_TYPE_NAME("neoverse-v1"), - ARM_CPU_TYPE_NAME("neoverse-n2"), -#endif /* TARGET_AARCH64 */ -#endif /* CONFIG_TCG */ -#ifdef TARGET_AARCH64 - ARM_CPU_TYPE_NAME("cortex-a53"), - ARM_CPU_TYPE_NAME("cortex-a57"), -#if defined(CONFIG_KVM) || defined(CONFIG_HVF) - ARM_CPU_TYPE_NAME("host"), -#endif /* CONFIG_KVM || CONFIG_HVF */ -#endif /* TARGET_AARCH64 */ - ARM_CPU_TYPE_NAME("max"), - NULL - }; mc->init = machvirt_init; /* Start with max_cpus set to 512, which is the maximum supported by KVM. @@ -3187,7 +3192,7 @@ static void virt_machine_class_init(ObjectClass *oc, void *data) #else mc->default_cpu_type = ARM_CPU_TYPE_NAME("max"); #endif - mc->valid_cpu_types = valid_cpu_types; + mc->get_valid_cpu_types = virt_get_valid_cpu_types; mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; mc->kvm_type = virt_kvm_type; mc->hvf_get_physical_address_range = virt_hvf_get_physical_address_range; -- 2.47.1 ^ permalink raw reply related [flat|nested] 66+ messages in thread
* Re: [RFC PATCH v4 12/19] hw/arm/virt: Register valid CPU types dynamically 2025-04-22 14:54 ` [RFC PATCH v4 12/19] hw/arm/virt: Register valid CPU types dynamically Philippe Mathieu-Daudé @ 2025-04-22 17:56 ` Richard Henderson 2025-04-22 18:10 ` Pierrick Bouvier 2025-04-22 18:18 ` Philippe Mathieu-Daudé 0 siblings, 2 replies; 66+ messages in thread From: Richard Henderson @ 2025-04-22 17:56 UTC (permalink / raw) To: Philippe Mathieu-Daudé, qemu-devel, Pierrick Bouvier; +Cc: Anton Johansson On 4/22/25 07:54, Philippe Mathieu-Daudé wrote: > +#ifdef CONFIG_TCG > + vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a7"))); > + vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a15"))); > +#ifdef TARGET_AARCH64 > + vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a35"))); > + vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a55"))); > + vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a72"))); > + vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a76"))); > + vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a710"))); > + vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("a64fx"))); > + vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-n1"))); > + vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-v1"))); > + vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-n2"))); > +#endif /* TARGET_AARCH64 */ Why do these need to be strdup'ed? Do you anticipate other instances where these names cannot be constructed at compile-time? r~ ^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [RFC PATCH v4 12/19] hw/arm/virt: Register valid CPU types dynamically 2025-04-22 17:56 ` Richard Henderson @ 2025-04-22 18:10 ` Pierrick Bouvier 2025-04-22 18:18 ` Philippe Mathieu-Daudé 1 sibling, 0 replies; 66+ messages in thread From: Pierrick Bouvier @ 2025-04-22 18:10 UTC (permalink / raw) To: Richard Henderson, Philippe Mathieu-Daudé, qemu-devel Cc: Anton Johansson On 4/22/25 10:56, Richard Henderson wrote: > On 4/22/25 07:54, Philippe Mathieu-Daudé wrote: >> +#ifdef CONFIG_TCG >> + vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a7"))); >> + vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a15"))); >> +#ifdef TARGET_AARCH64 >> + vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a35"))); >> + vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a55"))); >> + vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a72"))); >> + vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a76"))); >> + vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a710"))); >> + vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("a64fx"))); >> + vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-n1"))); >> + vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-v1"))); >> + vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-n2"))); >> +#endif /* TARGET_AARCH64 */ > > Why do these need to be strdup'ed? > > Do you anticipate other instances where these names cannot be constructed at compile-time? > It seems it would be more easy if get_valid_cpu_types simply return a const* char* const (same as existing valid_cpu_types), and caller does not have the responsibility to free it. This way, the list can be built either with a static array initializer, or with a dynamic GPtrArray, that we keep under a local static variable, so it has to be built only once. We can debate the leak introduced but I don't think it's really a problem. > > r~ ^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [RFC PATCH v4 12/19] hw/arm/virt: Register valid CPU types dynamically 2025-04-22 17:56 ` Richard Henderson 2025-04-22 18:10 ` Pierrick Bouvier @ 2025-04-22 18:18 ` Philippe Mathieu-Daudé 1 sibling, 0 replies; 66+ messages in thread From: Philippe Mathieu-Daudé @ 2025-04-22 18:18 UTC (permalink / raw) To: Richard Henderson, qemu-devel, Pierrick Bouvier; +Cc: Anton Johansson On 22/4/25 19:56, Richard Henderson wrote: > On 4/22/25 07:54, Philippe Mathieu-Daudé wrote: >> +#ifdef CONFIG_TCG >> + vct = g_slist_prepend(vct, >> g_strdup(ARM_CPU_TYPE_NAME("cortex-a7"))); >> + vct = g_slist_prepend(vct, >> g_strdup(ARM_CPU_TYPE_NAME("cortex-a15"))); >> +#ifdef TARGET_AARCH64 >> + vct = g_slist_prepend(vct, >> g_strdup(ARM_CPU_TYPE_NAME("cortex-a35"))); >> + vct = g_slist_prepend(vct, >> g_strdup(ARM_CPU_TYPE_NAME("cortex-a55"))); >> + vct = g_slist_prepend(vct, >> g_strdup(ARM_CPU_TYPE_NAME("cortex-a72"))); >> + vct = g_slist_prepend(vct, >> g_strdup(ARM_CPU_TYPE_NAME("cortex-a76"))); >> + vct = g_slist_prepend(vct, >> g_strdup(ARM_CPU_TYPE_NAME("cortex-a710"))); >> + vct = g_slist_prepend(vct, >> g_strdup(ARM_CPU_TYPE_NAME("a64fx"))); >> + vct = g_slist_prepend(vct, >> g_strdup(ARM_CPU_TYPE_NAME("neoverse-n1"))); >> + vct = g_slist_prepend(vct, >> g_strdup(ARM_CPU_TYPE_NAME("neoverse-v1"))); >> + vct = g_slist_prepend(vct, >> g_strdup(ARM_CPU_TYPE_NAME("neoverse-n2"))); >> +#endif /* TARGET_AARCH64 */ > > Why do these need to be strdup'ed? g_slist_prepend() expects non-const. > > Do you anticipate other instances where these names cannot be > constructed at compile-time? > > > r~ ^ permalink raw reply [flat|nested] 66+ messages in thread
* [RFC PATCH v4 13/19] hw/arm/virt: Check accelerator availability at runtime 2025-04-22 14:54 [RFC PATCH v4 00/19] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé ` (11 preceding siblings ...) 2025-04-22 14:54 ` [RFC PATCH v4 12/19] hw/arm/virt: Register valid CPU types dynamically Philippe Mathieu-Daudé @ 2025-04-22 14:54 ` Philippe Mathieu-Daudé 2025-04-22 17:56 ` Richard Henderson 2025-04-22 18:18 ` Pierrick Bouvier 2025-04-22 14:54 ` [RFC PATCH v4 14/19] qemu/target_info: Add %target_arch field to TargetInfo Philippe Mathieu-Daudé ` (5 subsequent siblings) 18 siblings, 2 replies; 66+ messages in thread From: Philippe Mathieu-Daudé @ 2025-04-22 14:54 UTC (permalink / raw) To: qemu-devel, Pierrick Bouvier; +Cc: Richard Henderson, Anton Johansson Replace compile-time check on CONFIG_{ACCEL} by runtime check on {accel}_enabled() helpers. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- hw/arm/virt.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index c6ae7cc1705..d7197958f7c 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -3134,7 +3134,7 @@ static GSList *virt_get_valid_cpu_types(const MachineState *ms) { GSList *vct = NULL; -#ifdef CONFIG_TCG + if (tcg_enabled()) { vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a7"))); vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a15"))); #ifdef TARGET_AARCH64 @@ -3148,13 +3148,13 @@ static GSList *virt_get_valid_cpu_types(const MachineState *ms) vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-v1"))); vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-n2"))); #endif /* TARGET_AARCH64 */ -#endif /* CONFIG_TCG */ + } #ifdef TARGET_AARCH64 vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a53"))); vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a57"))); -#if defined(CONFIG_KVM) || defined(CONFIG_HVF) + if (kvm_enabled() || hvf_enabled()) { vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("host"))); -#endif /* CONFIG_KVM || CONFIG_HVF */ + } #endif /* TARGET_AARCH64 */ vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("max"))); -- 2.47.1 ^ permalink raw reply related [flat|nested] 66+ messages in thread
* Re: [RFC PATCH v4 13/19] hw/arm/virt: Check accelerator availability at runtime 2025-04-22 14:54 ` [RFC PATCH v4 13/19] hw/arm/virt: Check accelerator availability at runtime Philippe Mathieu-Daudé @ 2025-04-22 17:56 ` Richard Henderson 2025-04-22 18:18 ` Pierrick Bouvier 1 sibling, 0 replies; 66+ messages in thread From: Richard Henderson @ 2025-04-22 17:56 UTC (permalink / raw) To: Philippe Mathieu-Daudé, qemu-devel, Pierrick Bouvier; +Cc: Anton Johansson On 4/22/25 07:54, Philippe Mathieu-Daudé wrote: > Replace compile-time check on CONFIG_{ACCEL} by > runtime check on {accel}_enabled() helpers. > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- > hw/arm/virt.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~ > > diff --git a/hw/arm/virt.c b/hw/arm/virt.c > index c6ae7cc1705..d7197958f7c 100644 > --- a/hw/arm/virt.c > +++ b/hw/arm/virt.c > @@ -3134,7 +3134,7 @@ static GSList *virt_get_valid_cpu_types(const MachineState *ms) > { > GSList *vct = NULL; > > -#ifdef CONFIG_TCG > + if (tcg_enabled()) { > vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a7"))); > vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a15"))); > #ifdef TARGET_AARCH64 > @@ -3148,13 +3148,13 @@ static GSList *virt_get_valid_cpu_types(const MachineState *ms) > vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-v1"))); > vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-n2"))); > #endif /* TARGET_AARCH64 */ > -#endif /* CONFIG_TCG */ > + } > #ifdef TARGET_AARCH64 > vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a53"))); > vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a57"))); > -#if defined(CONFIG_KVM) || defined(CONFIG_HVF) > + if (kvm_enabled() || hvf_enabled()) { > vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("host"))); > -#endif /* CONFIG_KVM || CONFIG_HVF */ > + } > #endif /* TARGET_AARCH64 */ > vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("max"))); > ^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [RFC PATCH v4 13/19] hw/arm/virt: Check accelerator availability at runtime 2025-04-22 14:54 ` [RFC PATCH v4 13/19] hw/arm/virt: Check accelerator availability at runtime Philippe Mathieu-Daudé 2025-04-22 17:56 ` Richard Henderson @ 2025-04-22 18:18 ` Pierrick Bouvier 1 sibling, 0 replies; 66+ messages in thread From: Pierrick Bouvier @ 2025-04-22 18:18 UTC (permalink / raw) To: Philippe Mathieu-Daudé, qemu-devel Cc: Richard Henderson, Anton Johansson On 4/22/25 07:54, Philippe Mathieu-Daudé wrote: > Replace compile-time check on CONFIG_{ACCEL} by > runtime check on {accel}_enabled() helpers. > Maybe we can add it the description why it works: since get_valid_cpu_types is called after accelerator initialization. qmp_x_exit_preconfig + qemu_init_board + machine_run_board_init + is_cpu_type_supported which is called after: configure_accelerators It was an issue with the first approach building the list before main(), so worth mentioning. > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- > hw/arm/virt.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/hw/arm/virt.c b/hw/arm/virt.c > index c6ae7cc1705..d7197958f7c 100644 > --- a/hw/arm/virt.c > +++ b/hw/arm/virt.c > @@ -3134,7 +3134,7 @@ static GSList *virt_get_valid_cpu_types(const MachineState *ms) > { > GSList *vct = NULL; > > -#ifdef CONFIG_TCG > + if (tcg_enabled()) { > vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a7"))); > vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a15"))); > #ifdef TARGET_AARCH64 > @@ -3148,13 +3148,13 @@ static GSList *virt_get_valid_cpu_types(const MachineState *ms) > vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-v1"))); > vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-n2"))); > #endif /* TARGET_AARCH64 */ > -#endif /* CONFIG_TCG */ > + } > #ifdef TARGET_AARCH64 > vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a53"))); > vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a57"))); > -#if defined(CONFIG_KVM) || defined(CONFIG_HVF) > + if (kvm_enabled() || hvf_enabled()) { > vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("host"))); > -#endif /* CONFIG_KVM || CONFIG_HVF */ > + } > #endif /* TARGET_AARCH64 */ > vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("max"))); > ^ permalink raw reply [flat|nested] 66+ messages in thread
* [RFC PATCH v4 14/19] qemu/target_info: Add %target_arch field to TargetInfo 2025-04-22 14:54 [RFC PATCH v4 00/19] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé ` (12 preceding siblings ...) 2025-04-22 14:54 ` [RFC PATCH v4 13/19] hw/arm/virt: Check accelerator availability at runtime Philippe Mathieu-Daudé @ 2025-04-22 14:54 ` Philippe Mathieu-Daudé 2025-04-22 17:46 ` Richard Henderson 2025-04-22 18:20 ` Pierrick Bouvier 2025-04-22 14:54 ` [RFC PATCH v4 15/19] qemu/target_info: Add target_aarch64() helper Philippe Mathieu-Daudé ` (4 subsequent siblings) 18 siblings, 2 replies; 66+ messages in thread From: Philippe Mathieu-Daudé @ 2025-04-22 14:54 UTC (permalink / raw) To: qemu-devel, Pierrick Bouvier; +Cc: Richard Henderson, Anton Johansson Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- include/qemu/target-info-impl.h | 4 ++++ configs/targets/aarch64-softmmu.c | 1 + configs/targets/arm-softmmu.c | 1 + target-info-stub.c | 1 + 4 files changed, 7 insertions(+) diff --git a/include/qemu/target-info-impl.h b/include/qemu/target-info-impl.h index 4ef54c5136a..e5cd169b49a 100644 --- a/include/qemu/target-info-impl.h +++ b/include/qemu/target-info-impl.h @@ -10,12 +10,16 @@ #define QEMU_TARGET_INFO_IMPL_H #include "qemu/target-info.h" +#include "qapi/qapi-types-machine.h" typedef struct TargetInfo { /* runtime equivalent of TARGET_NAME definition */ const char *const target_name; + /* related to TARGET_ARCH definition */ + SysEmuTarget target_arch; + /* QOM typename machines for this binary must implement */ const char *const machine_typename; diff --git a/configs/targets/aarch64-softmmu.c b/configs/targets/aarch64-softmmu.c index 375e6fa0b7b..ff89401ea34 100644 --- a/configs/targets/aarch64-softmmu.c +++ b/configs/targets/aarch64-softmmu.c @@ -13,6 +13,7 @@ static const TargetInfo target_info_aarch64_system = { .target_name = "aarch64", + .target_arch = SYS_EMU_TARGET_AARCH64, .machine_typename = TYPE_TARGET_AARCH64_MACHINE, }; diff --git a/configs/targets/arm-softmmu.c b/configs/targets/arm-softmmu.c index d4acdae64f3..22ec9e4faa3 100644 --- a/configs/targets/arm-softmmu.c +++ b/configs/targets/arm-softmmu.c @@ -13,6 +13,7 @@ static const TargetInfo target_info_arm_system = { .target_name = "arm", + .target_arch = SYS_EMU_TARGET_ARM, .machine_typename = TYPE_TARGET_ARM_MACHINE, }; diff --git a/target-info-stub.c b/target-info-stub.c index 218e5898e7f..e573f5c1975 100644 --- a/target-info-stub.c +++ b/target-info-stub.c @@ -12,6 +12,7 @@ static const TargetInfo target_info_stub = { .target_name = TARGET_NAME, + .target_arch = -1, .machine_typename = TYPE_MACHINE, }; -- 2.47.1 ^ permalink raw reply related [flat|nested] 66+ messages in thread
* Re: [RFC PATCH v4 14/19] qemu/target_info: Add %target_arch field to TargetInfo 2025-04-22 14:54 ` [RFC PATCH v4 14/19] qemu/target_info: Add %target_arch field to TargetInfo Philippe Mathieu-Daudé @ 2025-04-22 17:46 ` Richard Henderson 2025-04-22 18:20 ` Pierrick Bouvier 1 sibling, 0 replies; 66+ messages in thread From: Richard Henderson @ 2025-04-22 17:46 UTC (permalink / raw) To: Philippe Mathieu-Daudé, qemu-devel, Pierrick Bouvier; +Cc: Anton Johansson On 4/22/25 07:54, Philippe Mathieu-Daudé wrote: > Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org> > --- > include/qemu/target-info-impl.h | 4 ++++ > configs/targets/aarch64-softmmu.c | 1 + > configs/targets/arm-softmmu.c | 1 + > target-info-stub.c | 1 + > 4 files changed, 7 insertions(+) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~ ^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [RFC PATCH v4 14/19] qemu/target_info: Add %target_arch field to TargetInfo 2025-04-22 14:54 ` [RFC PATCH v4 14/19] qemu/target_info: Add %target_arch field to TargetInfo Philippe Mathieu-Daudé 2025-04-22 17:46 ` Richard Henderson @ 2025-04-22 18:20 ` Pierrick Bouvier 2025-04-22 18:24 ` Philippe Mathieu-Daudé 1 sibling, 1 reply; 66+ messages in thread From: Pierrick Bouvier @ 2025-04-22 18:20 UTC (permalink / raw) To: Philippe Mathieu-Daudé, qemu-devel Cc: Richard Henderson, Anton Johansson On 4/22/25 07:54, Philippe Mathieu-Daudé wrote: > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- > include/qemu/target-info-impl.h | 4 ++++ > configs/targets/aarch64-softmmu.c | 1 + > configs/targets/arm-softmmu.c | 1 + > target-info-stub.c | 1 + > 4 files changed, 7 insertions(+) > > diff --git a/include/qemu/target-info-impl.h b/include/qemu/target-info-impl.h > index 4ef54c5136a..e5cd169b49a 100644 > --- a/include/qemu/target-info-impl.h > +++ b/include/qemu/target-info-impl.h > @@ -10,12 +10,16 @@ > #define QEMU_TARGET_INFO_IMPL_H > > #include "qemu/target-info.h" > +#include "qapi/qapi-types-machine.h" > > typedef struct TargetInfo { > > /* runtime equivalent of TARGET_NAME definition */ > const char *const target_name; > > + /* related to TARGET_ARCH definition */ > + SysEmuTarget target_arch; > + > /* QOM typename machines for this binary must implement */ > const char *const machine_typename; > > diff --git a/configs/targets/aarch64-softmmu.c b/configs/targets/aarch64-softmmu.c > index 375e6fa0b7b..ff89401ea34 100644 > --- a/configs/targets/aarch64-softmmu.c > +++ b/configs/targets/aarch64-softmmu.c > @@ -13,6 +13,7 @@ > > static const TargetInfo target_info_aarch64_system = { > .target_name = "aarch64", > + .target_arch = SYS_EMU_TARGET_AARCH64, > .machine_typename = TYPE_TARGET_AARCH64_MACHINE, > }; > > diff --git a/configs/targets/arm-softmmu.c b/configs/targets/arm-softmmu.c > index d4acdae64f3..22ec9e4faa3 100644 > --- a/configs/targets/arm-softmmu.c > +++ b/configs/targets/arm-softmmu.c > @@ -13,6 +13,7 @@ > > static const TargetInfo target_info_arm_system = { > .target_name = "arm", > + .target_arch = SYS_EMU_TARGET_ARM, > .machine_typename = TYPE_TARGET_ARM_MACHINE, > }; > > diff --git a/target-info-stub.c b/target-info-stub.c > index 218e5898e7f..e573f5c1975 100644 > --- a/target-info-stub.c > +++ b/target-info-stub.c > @@ -12,6 +12,7 @@ > > static const TargetInfo target_info_stub = { > .target_name = TARGET_NAME, > + .target_arch = -1, I think we should have a full ifdef ladder here, to handle all architectures. Setting -1 is not a safe default. > .machine_typename = TYPE_MACHINE, > }; > ^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [RFC PATCH v4 14/19] qemu/target_info: Add %target_arch field to TargetInfo 2025-04-22 18:20 ` Pierrick Bouvier @ 2025-04-22 18:24 ` Philippe Mathieu-Daudé 2025-04-22 18:30 ` Pierrick Bouvier 0 siblings, 1 reply; 66+ messages in thread From: Philippe Mathieu-Daudé @ 2025-04-22 18:24 UTC (permalink / raw) To: Pierrick Bouvier, qemu-devel; +Cc: Richard Henderson, Anton Johansson On 22/4/25 20:20, Pierrick Bouvier wrote: > On 4/22/25 07:54, Philippe Mathieu-Daudé wrote: >> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> >> --- >> include/qemu/target-info-impl.h | 4 ++++ >> configs/targets/aarch64-softmmu.c | 1 + >> configs/targets/arm-softmmu.c | 1 + >> target-info-stub.c | 1 + >> 4 files changed, 7 insertions(+) >> >> diff --git a/include/qemu/target-info-impl.h b/include/qemu/target- >> info-impl.h >> index 4ef54c5136a..e5cd169b49a 100644 >> --- a/include/qemu/target-info-impl.h >> +++ b/include/qemu/target-info-impl.h >> @@ -10,12 +10,16 @@ >> #define QEMU_TARGET_INFO_IMPL_H >> #include "qemu/target-info.h" >> +#include "qapi/qapi-types-machine.h" >> typedef struct TargetInfo { >> /* runtime equivalent of TARGET_NAME definition */ >> const char *const target_name; >> + /* related to TARGET_ARCH definition */ >> + SysEmuTarget target_arch; >> + >> /* QOM typename machines for this binary must implement */ >> const char *const machine_typename; >> diff --git a/configs/targets/aarch64-softmmu.c b/configs/targets/ >> aarch64-softmmu.c >> index 375e6fa0b7b..ff89401ea34 100644 >> --- a/configs/targets/aarch64-softmmu.c >> +++ b/configs/targets/aarch64-softmmu.c >> @@ -13,6 +13,7 @@ >> static const TargetInfo target_info_aarch64_system = { >> .target_name = "aarch64", >> + .target_arch = SYS_EMU_TARGET_AARCH64, >> .machine_typename = TYPE_TARGET_AARCH64_MACHINE, >> }; >> diff --git a/configs/targets/arm-softmmu.c b/configs/targets/arm- >> softmmu.c >> index d4acdae64f3..22ec9e4faa3 100644 >> --- a/configs/targets/arm-softmmu.c >> +++ b/configs/targets/arm-softmmu.c >> @@ -13,6 +13,7 @@ >> static const TargetInfo target_info_arm_system = { >> .target_name = "arm", >> + .target_arch = SYS_EMU_TARGET_ARM, >> .machine_typename = TYPE_TARGET_ARM_MACHINE, >> }; >> diff --git a/target-info-stub.c b/target-info-stub.c >> index 218e5898e7f..e573f5c1975 100644 >> --- a/target-info-stub.c >> +++ b/target-info-stub.c >> @@ -12,6 +12,7 @@ >> static const TargetInfo target_info_stub = { >> .target_name = TARGET_NAME, >> + .target_arch = -1, > > I think we should have a full ifdef ladder here, to handle all > architectures. Setting -1 is not a safe default. TargetInfo definition is internal to "qemu/target-info-impl.h", otherwise its type is forward-declared as opaque. > >> .machine_typename = TYPE_MACHINE, >> }; > ^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [RFC PATCH v4 14/19] qemu/target_info: Add %target_arch field to TargetInfo 2025-04-22 18:24 ` Philippe Mathieu-Daudé @ 2025-04-22 18:30 ` Pierrick Bouvier 2025-04-23 5:34 ` Philippe Mathieu-Daudé 0 siblings, 1 reply; 66+ messages in thread From: Pierrick Bouvier @ 2025-04-22 18:30 UTC (permalink / raw) To: Philippe Mathieu-Daudé, qemu-devel Cc: Richard Henderson, Anton Johansson On 4/22/25 11:24, Philippe Mathieu-Daudé wrote: > On 22/4/25 20:20, Pierrick Bouvier wrote: >> On 4/22/25 07:54, Philippe Mathieu-Daudé wrote: >>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> >>> --- >>> include/qemu/target-info-impl.h | 4 ++++ >>> configs/targets/aarch64-softmmu.c | 1 + >>> configs/targets/arm-softmmu.c | 1 + >>> target-info-stub.c | 1 + >>> 4 files changed, 7 insertions(+) >>> >>> diff --git a/include/qemu/target-info-impl.h b/include/qemu/target- >>> info-impl.h >>> index 4ef54c5136a..e5cd169b49a 100644 >>> --- a/include/qemu/target-info-impl.h >>> +++ b/include/qemu/target-info-impl.h >>> @@ -10,12 +10,16 @@ >>> #define QEMU_TARGET_INFO_IMPL_H >>> #include "qemu/target-info.h" >>> +#include "qapi/qapi-types-machine.h" >>> typedef struct TargetInfo { >>> /* runtime equivalent of TARGET_NAME definition */ >>> const char *const target_name; >>> + /* related to TARGET_ARCH definition */ >>> + SysEmuTarget target_arch; >>> + >>> /* QOM typename machines for this binary must implement */ >>> const char *const machine_typename; >>> diff --git a/configs/targets/aarch64-softmmu.c b/configs/targets/ >>> aarch64-softmmu.c >>> index 375e6fa0b7b..ff89401ea34 100644 >>> --- a/configs/targets/aarch64-softmmu.c >>> +++ b/configs/targets/aarch64-softmmu.c >>> @@ -13,6 +13,7 @@ >>> static const TargetInfo target_info_aarch64_system = { >>> .target_name = "aarch64", >>> + .target_arch = SYS_EMU_TARGET_AARCH64, >>> .machine_typename = TYPE_TARGET_AARCH64_MACHINE, >>> }; >>> diff --git a/configs/targets/arm-softmmu.c b/configs/targets/arm- >>> softmmu.c >>> index d4acdae64f3..22ec9e4faa3 100644 >>> --- a/configs/targets/arm-softmmu.c >>> +++ b/configs/targets/arm-softmmu.c >>> @@ -13,6 +13,7 @@ >>> static const TargetInfo target_info_arm_system = { >>> .target_name = "arm", >>> + .target_arch = SYS_EMU_TARGET_ARM, >>> .machine_typename = TYPE_TARGET_ARM_MACHINE, >>> }; >>> diff --git a/target-info-stub.c b/target-info-stub.c >>> index 218e5898e7f..e573f5c1975 100644 >>> --- a/target-info-stub.c >>> +++ b/target-info-stub.c >>> @@ -12,6 +12,7 @@ >>> static const TargetInfo target_info_stub = { >>> .target_name = TARGET_NAME, >>> + .target_arch = -1, >> >> I think we should have a full ifdef ladder here, to handle all >> architectures. Setting -1 is not a safe default. > > TargetInfo definition is internal to "qemu/target-info-impl.h", > otherwise its type is forward-declared as opaque. > Fine, but we need to be able to access to target_arch(), which returns the enum value, without having to deal with -1 situation, which is not a proper enum value. switch (target_arch()) { case SYS_EMU_TARGET_ARM: case SYS_EMU_TARGET_AARCH64: ... default: break; } >> >>> .machine_typename = TYPE_MACHINE, >>> }; >> > ^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [RFC PATCH v4 14/19] qemu/target_info: Add %target_arch field to TargetInfo 2025-04-22 18:30 ` Pierrick Bouvier @ 2025-04-23 5:34 ` Philippe Mathieu-Daudé 2025-04-23 6:24 ` Pierrick Bouvier 0 siblings, 1 reply; 66+ messages in thread From: Philippe Mathieu-Daudé @ 2025-04-23 5:34 UTC (permalink / raw) To: Pierrick Bouvier, qemu-devel; +Cc: Richard Henderson, Anton Johansson On 22/4/25 20:30, Pierrick Bouvier wrote: > On 4/22/25 11:24, Philippe Mathieu-Daudé wrote: >> On 22/4/25 20:20, Pierrick Bouvier wrote: >>> On 4/22/25 07:54, Philippe Mathieu-Daudé wrote: >>>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> >>>> --- >>>> include/qemu/target-info-impl.h | 4 ++++ >>>> configs/targets/aarch64-softmmu.c | 1 + >>>> configs/targets/arm-softmmu.c | 1 + >>>> target-info-stub.c | 1 + >>>> 4 files changed, 7 insertions(+) >>>> >>>> diff --git a/include/qemu/target-info-impl.h b/include/qemu/target- >>>> info-impl.h >>>> index 4ef54c5136a..e5cd169b49a 100644 >>>> --- a/include/qemu/target-info-impl.h >>>> +++ b/include/qemu/target-info-impl.h >>>> @@ -10,12 +10,16 @@ >>>> #define QEMU_TARGET_INFO_IMPL_H >>>> #include "qemu/target-info.h" >>>> +#include "qapi/qapi-types-machine.h" >>>> typedef struct TargetInfo { >>>> /* runtime equivalent of TARGET_NAME definition */ >>>> const char *const target_name; >>>> + /* related to TARGET_ARCH definition */ >>>> + SysEmuTarget target_arch; >>>> + >>>> /* QOM typename machines for this binary must implement */ >>>> const char *const machine_typename; >>>> diff --git a/configs/targets/aarch64-softmmu.c b/configs/targets/ >>>> aarch64-softmmu.c >>>> index 375e6fa0b7b..ff89401ea34 100644 >>>> --- a/configs/targets/aarch64-softmmu.c >>>> +++ b/configs/targets/aarch64-softmmu.c >>>> @@ -13,6 +13,7 @@ >>>> static const TargetInfo target_info_aarch64_system = { >>>> .target_name = "aarch64", >>>> + .target_arch = SYS_EMU_TARGET_AARCH64, >>>> .machine_typename = TYPE_TARGET_AARCH64_MACHINE, >>>> }; >>>> diff --git a/configs/targets/arm-softmmu.c b/configs/targets/arm- >>>> softmmu.c >>>> index d4acdae64f3..22ec9e4faa3 100644 >>>> --- a/configs/targets/arm-softmmu.c >>>> +++ b/configs/targets/arm-softmmu.c >>>> @@ -13,6 +13,7 @@ >>>> static const TargetInfo target_info_arm_system = { >>>> .target_name = "arm", >>>> + .target_arch = SYS_EMU_TARGET_ARM, >>>> .machine_typename = TYPE_TARGET_ARM_MACHINE, >>>> }; >>>> diff --git a/target-info-stub.c b/target-info-stub.c >>>> index 218e5898e7f..e573f5c1975 100644 >>>> --- a/target-info-stub.c >>>> +++ b/target-info-stub.c >>>> @@ -12,6 +12,7 @@ >>>> static const TargetInfo target_info_stub = { >>>> .target_name = TARGET_NAME, >>>> + .target_arch = -1, >>> >>> I think we should have a full ifdef ladder here, to handle all >>> architectures. Setting -1 is not a safe default. >> >> TargetInfo definition is internal to "qemu/target-info-impl.h", >> otherwise its type is forward-declared as opaque. >> > > Fine, but we need to be able to access to target_arch(), which returns > the enum value, without having to deal with -1 situation, which is not a > proper enum value. > > switch (target_arch()) { > case SYS_EMU_TARGET_ARM: > case SYS_EMU_TARGET_AARCH64: > ... > default: > break; > } I didn't mentioned that because in https://lore.kernel.org/qemu-devel/3242cee6-7485-4958-a198-38d0fc68e8cd@linaro.org/ you said: At this point, I would like to focus on having a first version of TargetInfo API, and not reviewing any other changes, as things may be modified, and they would need to be reviewed again. It's hard to follow the same abstraction done multiple times in multiple series. What is your "full ifdef ladder" suggestion to avoid -1? ^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [RFC PATCH v4 14/19] qemu/target_info: Add %target_arch field to TargetInfo 2025-04-23 5:34 ` Philippe Mathieu-Daudé @ 2025-04-23 6:24 ` Pierrick Bouvier 2025-04-23 6:28 ` Pierrick Bouvier 2025-04-23 9:14 ` Philippe Mathieu-Daudé 0 siblings, 2 replies; 66+ messages in thread From: Pierrick Bouvier @ 2025-04-23 6:24 UTC (permalink / raw) To: Philippe Mathieu-Daudé, qemu-devel Cc: Richard Henderson, Anton Johansson On 4/22/25 22:34, Philippe Mathieu-Daudé wrote: > On 22/4/25 20:30, Pierrick Bouvier wrote: >> On 4/22/25 11:24, Philippe Mathieu-Daudé wrote: >>> On 22/4/25 20:20, Pierrick Bouvier wrote: >>>> On 4/22/25 07:54, Philippe Mathieu-Daudé wrote: >>>>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> >>>>> --- >>>>> include/qemu/target-info-impl.h | 4 ++++ >>>>> configs/targets/aarch64-softmmu.c | 1 + >>>>> configs/targets/arm-softmmu.c | 1 + >>>>> target-info-stub.c | 1 + >>>>> 4 files changed, 7 insertions(+) >>>>> >>>>> diff --git a/include/qemu/target-info-impl.h b/include/qemu/target- >>>>> info-impl.h >>>>> index 4ef54c5136a..e5cd169b49a 100644 >>>>> --- a/include/qemu/target-info-impl.h >>>>> +++ b/include/qemu/target-info-impl.h >>>>> @@ -10,12 +10,16 @@ >>>>> #define QEMU_TARGET_INFO_IMPL_H >>>>> #include "qemu/target-info.h" >>>>> +#include "qapi/qapi-types-machine.h" >>>>> typedef struct TargetInfo { >>>>> /* runtime equivalent of TARGET_NAME definition */ >>>>> const char *const target_name; >>>>> + /* related to TARGET_ARCH definition */ >>>>> + SysEmuTarget target_arch; >>>>> + >>>>> /* QOM typename machines for this binary must implement */ >>>>> const char *const machine_typename; >>>>> diff --git a/configs/targets/aarch64-softmmu.c b/configs/targets/ >>>>> aarch64-softmmu.c >>>>> index 375e6fa0b7b..ff89401ea34 100644 >>>>> --- a/configs/targets/aarch64-softmmu.c >>>>> +++ b/configs/targets/aarch64-softmmu.c >>>>> @@ -13,6 +13,7 @@ >>>>> static const TargetInfo target_info_aarch64_system = { >>>>> .target_name = "aarch64", >>>>> + .target_arch = SYS_EMU_TARGET_AARCH64, >>>>> .machine_typename = TYPE_TARGET_AARCH64_MACHINE, >>>>> }; >>>>> diff --git a/configs/targets/arm-softmmu.c b/configs/targets/arm- >>>>> softmmu.c >>>>> index d4acdae64f3..22ec9e4faa3 100644 >>>>> --- a/configs/targets/arm-softmmu.c >>>>> +++ b/configs/targets/arm-softmmu.c >>>>> @@ -13,6 +13,7 @@ >>>>> static const TargetInfo target_info_arm_system = { >>>>> .target_name = "arm", >>>>> + .target_arch = SYS_EMU_TARGET_ARM, >>>>> .machine_typename = TYPE_TARGET_ARM_MACHINE, >>>>> }; >>>>> diff --git a/target-info-stub.c b/target-info-stub.c >>>>> index 218e5898e7f..e573f5c1975 100644 >>>>> --- a/target-info-stub.c >>>>> +++ b/target-info-stub.c >>>>> @@ -12,6 +12,7 @@ >>>>> static const TargetInfo target_info_stub = { >>>>> .target_name = TARGET_NAME, >>>>> + .target_arch = -1, >>>> >>>> I think we should have a full ifdef ladder here, to handle all >>>> architectures. Setting -1 is not a safe default. >>> >>> TargetInfo definition is internal to "qemu/target-info-impl.h", >>> otherwise its type is forward-declared as opaque. >>> >> >> Fine, but we need to be able to access to target_arch(), which returns >> the enum value, without having to deal with -1 situation, which is not a >> proper enum value. >> >> switch (target_arch()) { >> case SYS_EMU_TARGET_ARM: >> case SYS_EMU_TARGET_AARCH64: >> ... >> default: >> break; >> } > > I didn't mentioned that because in > https://lore.kernel.org/qemu-devel/3242cee6-7485-4958-a198-38d0fc68e8cd@linaro.org/ > you said: > > At this point, I would like to focus on having a first version of > TargetInfo API, and not reviewing any other changes, as things may > be modified, and they would need to be reviewed again. It's hard > to follow the same abstraction done multiple times in multiple series. > > What is your "full ifdef ladder" suggestion to avoid -1? #ifdef TARGET_AARCH64 # define TARGET_ARCH SYS_EMU_TARGET_AARCH64 #elif TARGET_ARCH_ALPHA # define TARGET_ARCH SYS_EMU_TARGET_ALPHA ... #else #error Target architecture can't be detected #endif static const TargetInfo target_info_stub = { ... .target_arch = TARGET_ARCH; ... } One important stuff is to make sure we treat correctly bitness variants of a given arch: TARGET_AARCH64 should be tested *before* TARGET_ARM, and same for other base architectures. Besides that, it's straightforward, and we can easily integrate that in this series. ^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [RFC PATCH v4 14/19] qemu/target_info: Add %target_arch field to TargetInfo 2025-04-23 6:24 ` Pierrick Bouvier @ 2025-04-23 6:28 ` Pierrick Bouvier 2025-04-23 9:14 ` Philippe Mathieu-Daudé 1 sibling, 0 replies; 66+ messages in thread From: Pierrick Bouvier @ 2025-04-23 6:28 UTC (permalink / raw) To: Philippe Mathieu-Daudé, qemu-devel Cc: Richard Henderson, Anton Johansson On 4/22/25 23:24, Pierrick Bouvier wrote: > On 4/22/25 22:34, Philippe Mathieu-Daudé wrote: >> On 22/4/25 20:30, Pierrick Bouvier wrote: >>> On 4/22/25 11:24, Philippe Mathieu-Daudé wrote: >>>> On 22/4/25 20:20, Pierrick Bouvier wrote: >>>>> On 4/22/25 07:54, Philippe Mathieu-Daudé wrote: >>>>>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> >>>>>> --- >>>>>> include/qemu/target-info-impl.h | 4 ++++ >>>>>> configs/targets/aarch64-softmmu.c | 1 + >>>>>> configs/targets/arm-softmmu.c | 1 + >>>>>> target-info-stub.c | 1 + >>>>>> 4 files changed, 7 insertions(+) >>>>>> >>>>>> diff --git a/include/qemu/target-info-impl.h b/include/qemu/target- >>>>>> info-impl.h >>>>>> index 4ef54c5136a..e5cd169b49a 100644 >>>>>> --- a/include/qemu/target-info-impl.h >>>>>> +++ b/include/qemu/target-info-impl.h >>>>>> @@ -10,12 +10,16 @@ >>>>>> #define QEMU_TARGET_INFO_IMPL_H >>>>>> #include "qemu/target-info.h" >>>>>> +#include "qapi/qapi-types-machine.h" >>>>>> typedef struct TargetInfo { >>>>>> /* runtime equivalent of TARGET_NAME definition */ >>>>>> const char *const target_name; >>>>>> + /* related to TARGET_ARCH definition */ >>>>>> + SysEmuTarget target_arch; >>>>>> + >>>>>> /* QOM typename machines for this binary must implement */ >>>>>> const char *const machine_typename; >>>>>> diff --git a/configs/targets/aarch64-softmmu.c b/configs/targets/ >>>>>> aarch64-softmmu.c >>>>>> index 375e6fa0b7b..ff89401ea34 100644 >>>>>> --- a/configs/targets/aarch64-softmmu.c >>>>>> +++ b/configs/targets/aarch64-softmmu.c >>>>>> @@ -13,6 +13,7 @@ >>>>>> static const TargetInfo target_info_aarch64_system = { >>>>>> .target_name = "aarch64", >>>>>> + .target_arch = SYS_EMU_TARGET_AARCH64, >>>>>> .machine_typename = TYPE_TARGET_AARCH64_MACHINE, >>>>>> }; >>>>>> diff --git a/configs/targets/arm-softmmu.c b/configs/targets/arm- >>>>>> softmmu.c >>>>>> index d4acdae64f3..22ec9e4faa3 100644 >>>>>> --- a/configs/targets/arm-softmmu.c >>>>>> +++ b/configs/targets/arm-softmmu.c >>>>>> @@ -13,6 +13,7 @@ >>>>>> static const TargetInfo target_info_arm_system = { >>>>>> .target_name = "arm", >>>>>> + .target_arch = SYS_EMU_TARGET_ARM, >>>>>> .machine_typename = TYPE_TARGET_ARM_MACHINE, >>>>>> }; >>>>>> diff --git a/target-info-stub.c b/target-info-stub.c >>>>>> index 218e5898e7f..e573f5c1975 100644 >>>>>> --- a/target-info-stub.c >>>>>> +++ b/target-info-stub.c >>>>>> @@ -12,6 +12,7 @@ >>>>>> static const TargetInfo target_info_stub = { >>>>>> .target_name = TARGET_NAME, >>>>>> + .target_arch = -1, >>>>> >>>>> I think we should have a full ifdef ladder here, to handle all >>>>> architectures. Setting -1 is not a safe default. >>>> >>>> TargetInfo definition is internal to "qemu/target-info-impl.h", >>>> otherwise its type is forward-declared as opaque. >>>> >>> >>> Fine, but we need to be able to access to target_arch(), which returns >>> the enum value, without having to deal with -1 situation, which is not a >>> proper enum value. >>> >>> switch (target_arch()) { >>> case SYS_EMU_TARGET_ARM: >>> case SYS_EMU_TARGET_AARCH64: >>> ... >>> default: >>> break; >>> } >> >> I didn't mentioned that because in >> https://lore.kernel.org/qemu-devel/3242cee6-7485-4958-a198-38d0fc68e8cd@linaro.org/ >> you said: >> >> At this point, I would like to focus on having a first version of >> TargetInfo API, and not reviewing any other changes, as things may >> be modified, and they would need to be reviewed again. It's hard >> to follow the same abstraction done multiple times in multiple series. >> >> What is your "full ifdef ladder" suggestion to avoid -1? > > #ifdef TARGET_AARCH64 > # define TARGET_ARCH SYS_EMU_TARGET_AARCH64 > #elif TARGET_ARCH_ALPHA > # define TARGET_ARCH SYS_EMU_TARGET_ALPHA > ... > #else > #error Target architecture can't be detected > #endif > > static const TargetInfo target_info_stub = { > ... > .target_arch = TARGET_ARCH; > ... > } > To be complete, we should also add: static inline SysEmuTarget target_arch(void) { return target_info()->target_arch; } so it can be used by code later (QAPI generated files will need that, and virtio devices as you noticed). To make it used through the series, target_aarch64() can be rewritten: static inline bool target_aarch64(void) { return target_arch() == SYS_EMU_TARGET_AARCH64; } > One important stuff is to make sure we treat correctly bitness variants > of a given arch: TARGET_AARCH64 should be tested *before* TARGET_ARM, > and same for other base architectures. > Besides that, it's straightforward, and we can easily integrate that in > this series. ^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [RFC PATCH v4 14/19] qemu/target_info: Add %target_arch field to TargetInfo 2025-04-23 6:24 ` Pierrick Bouvier 2025-04-23 6:28 ` Pierrick Bouvier @ 2025-04-23 9:14 ` Philippe Mathieu-Daudé 2025-04-23 14:59 ` Pierrick Bouvier 1 sibling, 1 reply; 66+ messages in thread From: Philippe Mathieu-Daudé @ 2025-04-23 9:14 UTC (permalink / raw) To: Pierrick Bouvier, qemu-devel Cc: Richard Henderson, Anton Johansson, Markus Armbruster On 23/4/25 08:24, Pierrick Bouvier wrote: > On 4/22/25 22:34, Philippe Mathieu-Daudé wrote: >> On 22/4/25 20:30, Pierrick Bouvier wrote: >>> On 4/22/25 11:24, Philippe Mathieu-Daudé wrote: >>>> On 22/4/25 20:20, Pierrick Bouvier wrote: >>>>> On 4/22/25 07:54, Philippe Mathieu-Daudé wrote: >>>>>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> >>>>>> --- >>>>>> include/qemu/target-info-impl.h | 4 ++++ >>>>>> configs/targets/aarch64-softmmu.c | 1 + >>>>>> configs/targets/arm-softmmu.c | 1 + >>>>>> target-info-stub.c | 1 + >>>>>> 4 files changed, 7 insertions(+) >>>>>> >>>>>> diff --git a/include/qemu/target-info-impl.h b/include/qemu/target- >>>>>> info-impl.h >>>>>> index 4ef54c5136a..e5cd169b49a 100644 >>>>>> --- a/include/qemu/target-info-impl.h >>>>>> +++ b/include/qemu/target-info-impl.h >>>>>> @@ -10,12 +10,16 @@ >>>>>> #define QEMU_TARGET_INFO_IMPL_H >>>>>> #include "qemu/target-info.h" >>>>>> +#include "qapi/qapi-types-machine.h" >>>>>> typedef struct TargetInfo { >>>>>> /* runtime equivalent of TARGET_NAME definition */ >>>>>> const char *const target_name; >>>>>> + /* related to TARGET_ARCH definition */ >>>>>> + SysEmuTarget target_arch; >>>>>> + >>>>>> /* QOM typename machines for this binary must implement */ >>>>>> const char *const machine_typename; >>>>>> diff --git a/configs/targets/aarch64-softmmu.c b/configs/targets/ >>>>>> aarch64-softmmu.c >>>>>> index 375e6fa0b7b..ff89401ea34 100644 >>>>>> --- a/configs/targets/aarch64-softmmu.c >>>>>> +++ b/configs/targets/aarch64-softmmu.c >>>>>> @@ -13,6 +13,7 @@ >>>>>> static const TargetInfo target_info_aarch64_system = { >>>>>> .target_name = "aarch64", >>>>>> + .target_arch = SYS_EMU_TARGET_AARCH64, >>>>>> .machine_typename = TYPE_TARGET_AARCH64_MACHINE, >>>>>> }; >>>>>> diff --git a/configs/targets/arm-softmmu.c b/configs/targets/arm- >>>>>> softmmu.c >>>>>> index d4acdae64f3..22ec9e4faa3 100644 >>>>>> --- a/configs/targets/arm-softmmu.c >>>>>> +++ b/configs/targets/arm-softmmu.c >>>>>> @@ -13,6 +13,7 @@ >>>>>> static const TargetInfo target_info_arm_system = { >>>>>> .target_name = "arm", >>>>>> + .target_arch = SYS_EMU_TARGET_ARM, >>>>>> .machine_typename = TYPE_TARGET_ARM_MACHINE, >>>>>> }; >>>>>> diff --git a/target-info-stub.c b/target-info-stub.c >>>>>> index 218e5898e7f..e573f5c1975 100644 >>>>>> --- a/target-info-stub.c >>>>>> +++ b/target-info-stub.c >>>>>> @@ -12,6 +12,7 @@ >>>>>> static const TargetInfo target_info_stub = { >>>>>> .target_name = TARGET_NAME, >>>>>> + .target_arch = -1, >>>>> >>>>> I think we should have a full ifdef ladder here, to handle all >>>>> architectures. Setting -1 is not a safe default. >>>> >>>> TargetInfo definition is internal to "qemu/target-info-impl.h", >>>> otherwise its type is forward-declared as opaque. >>>> >>> >>> Fine, but we need to be able to access to target_arch(), which returns >>> the enum value, without having to deal with -1 situation, which is not a >>> proper enum value. >>> >>> switch (target_arch()) { >>> case SYS_EMU_TARGET_ARM: >>> case SYS_EMU_TARGET_AARCH64: >>> ... >>> default: >>> break; >>> } >> >> I didn't mentioned that because in >> https://lore.kernel.org/qemu-devel/3242cee6-7485-4958- >> a198-38d0fc68e8cd@linaro.org/ >> you said: >> >> At this point, I would like to focus on having a first version of >> TargetInfo API, and not reviewing any other changes, as things may >> be modified, and they would need to be reviewed again. It's hard >> to follow the same abstraction done multiple times in multiple >> series. >> >> What is your "full ifdef ladder" suggestion to avoid -1? > > #ifdef TARGET_AARCH64 > # define TARGET_ARCH SYS_EMU_TARGET_AARCH64 > #elif TARGET_ARCH_ALPHA > # define TARGET_ARCH SYS_EMU_TARGET_ALPHA > ... > #else > #error Target architecture can't be detected I'm sorry but I don't understand what we gain doing that. > #endif > > static const TargetInfo target_info_stub = { > ... > .target_arch = TARGET_ARCH; > ... > } > > One important stuff is to make sure we treat correctly bitness variants > of a given arch: TARGET_AARCH64 should be tested *before* TARGET_ARM, > and same for other base architectures. Thankfully we don't check for TARGET_ARM, so we don't have to implement a confusing target_arm() helper for the single-binary effort. When we get to heterogeneous emulation, I expect system ARM/Aarch64 to be merged as a single Aarch64 target (32-bit ARM being a CPU state), so the target_aarch64() should still be enough. > Besides that, it's straightforward, and we can easily integrate that in > this series. ^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [RFC PATCH v4 14/19] qemu/target_info: Add %target_arch field to TargetInfo 2025-04-23 9:14 ` Philippe Mathieu-Daudé @ 2025-04-23 14:59 ` Pierrick Bouvier 0 siblings, 0 replies; 66+ messages in thread From: Pierrick Bouvier @ 2025-04-23 14:59 UTC (permalink / raw) To: Philippe Mathieu-Daudé, qemu-devel Cc: Richard Henderson, Anton Johansson, Markus Armbruster On 4/23/25 02:14, Philippe Mathieu-Daudé wrote: > On 23/4/25 08:24, Pierrick Bouvier wrote: >> On 4/22/25 22:34, Philippe Mathieu-Daudé wrote: >>> On 22/4/25 20:30, Pierrick Bouvier wrote: >>>> On 4/22/25 11:24, Philippe Mathieu-Daudé wrote: >>>>> On 22/4/25 20:20, Pierrick Bouvier wrote: >>>>>> On 4/22/25 07:54, Philippe Mathieu-Daudé wrote: >>>>>>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> >>>>>>> --- >>>>>>> include/qemu/target-info-impl.h | 4 ++++ >>>>>>> configs/targets/aarch64-softmmu.c | 1 + >>>>>>> configs/targets/arm-softmmu.c | 1 + >>>>>>> target-info-stub.c | 1 + >>>>>>> 4 files changed, 7 insertions(+) >>>>>>> >>>>>>> diff --git a/include/qemu/target-info-impl.h b/include/qemu/target- >>>>>>> info-impl.h >>>>>>> index 4ef54c5136a..e5cd169b49a 100644 >>>>>>> --- a/include/qemu/target-info-impl.h >>>>>>> +++ b/include/qemu/target-info-impl.h >>>>>>> @@ -10,12 +10,16 @@ >>>>>>> #define QEMU_TARGET_INFO_IMPL_H >>>>>>> #include "qemu/target-info.h" >>>>>>> +#include "qapi/qapi-types-machine.h" >>>>>>> typedef struct TargetInfo { >>>>>>> /* runtime equivalent of TARGET_NAME definition */ >>>>>>> const char *const target_name; >>>>>>> + /* related to TARGET_ARCH definition */ >>>>>>> + SysEmuTarget target_arch; >>>>>>> + >>>>>>> /* QOM typename machines for this binary must implement */ >>>>>>> const char *const machine_typename; >>>>>>> diff --git a/configs/targets/aarch64-softmmu.c b/configs/targets/ >>>>>>> aarch64-softmmu.c >>>>>>> index 375e6fa0b7b..ff89401ea34 100644 >>>>>>> --- a/configs/targets/aarch64-softmmu.c >>>>>>> +++ b/configs/targets/aarch64-softmmu.c >>>>>>> @@ -13,6 +13,7 @@ >>>>>>> static const TargetInfo target_info_aarch64_system = { >>>>>>> .target_name = "aarch64", >>>>>>> + .target_arch = SYS_EMU_TARGET_AARCH64, >>>>>>> .machine_typename = TYPE_TARGET_AARCH64_MACHINE, >>>>>>> }; >>>>>>> diff --git a/configs/targets/arm-softmmu.c b/configs/targets/arm- >>>>>>> softmmu.c >>>>>>> index d4acdae64f3..22ec9e4faa3 100644 >>>>>>> --- a/configs/targets/arm-softmmu.c >>>>>>> +++ b/configs/targets/arm-softmmu.c >>>>>>> @@ -13,6 +13,7 @@ >>>>>>> static const TargetInfo target_info_arm_system = { >>>>>>> .target_name = "arm", >>>>>>> + .target_arch = SYS_EMU_TARGET_ARM, >>>>>>> .machine_typename = TYPE_TARGET_ARM_MACHINE, >>>>>>> }; >>>>>>> diff --git a/target-info-stub.c b/target-info-stub.c >>>>>>> index 218e5898e7f..e573f5c1975 100644 >>>>>>> --- a/target-info-stub.c >>>>>>> +++ b/target-info-stub.c >>>>>>> @@ -12,6 +12,7 @@ >>>>>>> static const TargetInfo target_info_stub = { >>>>>>> .target_name = TARGET_NAME, >>>>>>> + .target_arch = -1, >>>>>> >>>>>> I think we should have a full ifdef ladder here, to handle all >>>>>> architectures. Setting -1 is not a safe default. >>>>> >>>>> TargetInfo definition is internal to "qemu/target-info-impl.h", >>>>> otherwise its type is forward-declared as opaque. >>>>> >>>> >>>> Fine, but we need to be able to access to target_arch(), which returns >>>> the enum value, without having to deal with -1 situation, which is not a >>>> proper enum value. >>>> >>>> switch (target_arch()) { >>>> case SYS_EMU_TARGET_ARM: >>>> case SYS_EMU_TARGET_AARCH64: >>>> ... >>>> default: >>>> break; >>>> } >>> >>> I didn't mentioned that because in >>> https://lore.kernel.org/qemu-devel/3242cee6-7485-4958- >>> a198-38d0fc68e8cd@linaro.org/ >>> you said: >>> >>> At this point, I would like to focus on having a first version of >>> TargetInfo API, and not reviewing any other changes, as things may >>> be modified, and they would need to be reviewed again. It's hard >>> to follow the same abstraction done multiple times in multiple >>> series. >>> >>> What is your "full ifdef ladder" suggestion to avoid -1? >> >> #ifdef TARGET_AARCH64 >> # define TARGET_ARCH SYS_EMU_TARGET_AARCH64 >> #elif TARGET_ARCH_ALPHA >> # define TARGET_ARCH SYS_EMU_TARGET_ALPHA >> ... >> #else >> #error Target architecture can't be detected > > I'm sorry but I don't understand what we gain doing that. > For QAPI generated files, we'll need a various bunch of TARGET_X runtime conversion, to enable some commands only for targets. Some of the concerned targets are different from the one we focus on for single binary. My hope was to include target_arch() function in this series, so it's not a debate in next series that will touch to QAPI. In short, move the noise here and now compared to later with another unrelated topic, that will have a lot of heated opinions already. List of needed (target_()) for QAPI: TARGET_S390X TARGET_PPC TARGET_ARM TARGET_I386 TARGET_LOONGARCH64 TARGET_MIPS TARGET_RISCV TARGET_I386 If it's too much work on your side, would you be open that I provide this patch on top of your series, and that we include it with it? Thanks, Pierrick ^ permalink raw reply [flat|nested] 66+ messages in thread
* [RFC PATCH v4 15/19] qemu/target_info: Add target_aarch64() helper 2025-04-22 14:54 [RFC PATCH v4 00/19] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé ` (13 preceding siblings ...) 2025-04-22 14:54 ` [RFC PATCH v4 14/19] qemu/target_info: Add %target_arch field to TargetInfo Philippe Mathieu-Daudé @ 2025-04-22 14:54 ` Philippe Mathieu-Daudé 2025-04-22 17:46 ` Richard Henderson 2025-04-22 18:21 ` Pierrick Bouvier 2025-04-22 14:54 ` [RFC PATCH v4 16/19] hw/arm/virt: Replace TARGET_AARCH64 -> target_aarch64() Philippe Mathieu-Daudé ` (3 subsequent siblings) 18 siblings, 2 replies; 66+ messages in thread From: Philippe Mathieu-Daudé @ 2025-04-22 14:54 UTC (permalink / raw) To: qemu-devel, Pierrick Bouvier; +Cc: Richard Henderson, Anton Johansson Add a helper to distinct the binary is targetting Aarch64 or not. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- include/qemu/target-info.h | 7 +++++++ target-info.c | 5 +++++ 2 files changed, 12 insertions(+) diff --git a/include/qemu/target-info.h b/include/qemu/target-info.h index 0224b35b166..395c009baf2 100644 --- a/include/qemu/target-info.h +++ b/include/qemu/target-info.h @@ -24,4 +24,11 @@ const char *target_name(void); */ const char *target_machine_typename(void); +/** + * target_aarch64: + * + * Returns whether the target architecture is Aarch64. + */ +bool target_aarch64(void); + #endif diff --git a/target-info.c b/target-info.c index 0042769e3a2..7f1758ae34f 100644 --- a/target-info.c +++ b/target-info.c @@ -19,3 +19,8 @@ const char *target_machine_typename(void) { return target_info()->machine_typename; } + +bool target_aarch64(void) +{ + return target_info()->target_arch == SYS_EMU_TARGET_AARCH64; +} -- 2.47.1 ^ permalink raw reply related [flat|nested] 66+ messages in thread
* Re: [RFC PATCH v4 15/19] qemu/target_info: Add target_aarch64() helper 2025-04-22 14:54 ` [RFC PATCH v4 15/19] qemu/target_info: Add target_aarch64() helper Philippe Mathieu-Daudé @ 2025-04-22 17:46 ` Richard Henderson 2025-04-22 18:21 ` Pierrick Bouvier 1 sibling, 0 replies; 66+ messages in thread From: Richard Henderson @ 2025-04-22 17:46 UTC (permalink / raw) To: Philippe Mathieu-Daudé, qemu-devel, Pierrick Bouvier; +Cc: Anton Johansson On 4/22/25 07:54, Philippe Mathieu-Daudé wrote: > Add a helper to distinct the binary is targetting > Aarch64 or not. > > Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org> > --- > include/qemu/target-info.h | 7 +++++++ > target-info.c | 5 +++++ > 2 files changed, 12 insertions(+) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~ ^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [RFC PATCH v4 15/19] qemu/target_info: Add target_aarch64() helper 2025-04-22 14:54 ` [RFC PATCH v4 15/19] qemu/target_info: Add target_aarch64() helper Philippe Mathieu-Daudé 2025-04-22 17:46 ` Richard Henderson @ 2025-04-22 18:21 ` Pierrick Bouvier 1 sibling, 0 replies; 66+ messages in thread From: Pierrick Bouvier @ 2025-04-22 18:21 UTC (permalink / raw) To: Philippe Mathieu-Daudé, qemu-devel Cc: Richard Henderson, Anton Johansson On 4/22/25 07:54, Philippe Mathieu-Daudé wrote: > Add a helper to distinct the binary is targetting > Aarch64 or not. > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- > include/qemu/target-info.h | 7 +++++++ > target-info.c | 5 +++++ > 2 files changed, 12 insertions(+) > > diff --git a/include/qemu/target-info.h b/include/qemu/target-info.h > index 0224b35b166..395c009baf2 100644 > --- a/include/qemu/target-info.h > +++ b/include/qemu/target-info.h > @@ -24,4 +24,11 @@ const char *target_name(void); > */ > const char *target_machine_typename(void); > > +/** > + * target_aarch64: > + * > + * Returns whether the target architecture is Aarch64. > + */ > +bool target_aarch64(void); > + > #endif > diff --git a/target-info.c b/target-info.c > index 0042769e3a2..7f1758ae34f 100644 > --- a/target-info.c > +++ b/target-info.c > @@ -19,3 +19,8 @@ const char *target_machine_typename(void) > { > return target_info()->machine_typename; > } > + > +bool target_aarch64(void) > +{ > + return target_info()->target_arch == SYS_EMU_TARGET_AARCH64; > +} Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> ^ permalink raw reply [flat|nested] 66+ messages in thread
* [RFC PATCH v4 16/19] hw/arm/virt: Replace TARGET_AARCH64 -> target_aarch64() 2025-04-22 14:54 [RFC PATCH v4 00/19] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé ` (14 preceding siblings ...) 2025-04-22 14:54 ` [RFC PATCH v4 15/19] qemu/target_info: Add target_aarch64() helper Philippe Mathieu-Daudé @ 2025-04-22 14:54 ` Philippe Mathieu-Daudé 2025-04-22 17:47 ` Richard Henderson 2025-04-22 18:22 ` Pierrick Bouvier 2025-04-22 14:54 ` [RFC PATCH v4 17/19] hw/core: Get default_cpu_type calling machine_class_default_cpu_type() Philippe Mathieu-Daudé ` (2 subsequent siblings) 18 siblings, 2 replies; 66+ messages in thread From: Philippe Mathieu-Daudé @ 2025-04-22 14:54 UTC (permalink / raw) To: qemu-devel, Pierrick Bouvier; +Cc: Richard Henderson, Anton Johansson Replace the target-specific TARGET_AARCH64 definition by a call to the generic target_aarch64() helper. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- This removes the last TARGET_AARCH64 in hw/arm/. --- hw/arm/virt.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index d7197958f7c..4e11272a3ac 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -32,6 +32,7 @@ #include "qemu/datadir.h" #include "qemu/units.h" #include "qemu/option.h" +#include "qemu/target-info.h" #include "monitor/qdev.h" #include "hw/sysbus.h" #include "hw/arm/boot.h" @@ -3137,7 +3138,8 @@ static GSList *virt_get_valid_cpu_types(const MachineState *ms) if (tcg_enabled()) { vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a7"))); vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a15"))); -#ifdef TARGET_AARCH64 + } + if (tcg_enabled() && target_aarch64()) { vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a35"))); vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a55"))); vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a72"))); @@ -3147,15 +3149,14 @@ static GSList *virt_get_valid_cpu_types(const MachineState *ms) vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-n1"))); vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-v1"))); vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-n2"))); -#endif /* TARGET_AARCH64 */ } -#ifdef TARGET_AARCH64 + if (target_aarch64()) { vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a53"))); vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a57"))); if (kvm_enabled() || hvf_enabled()) { vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("host"))); } -#endif /* TARGET_AARCH64 */ + } vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("max"))); return vct; -- 2.47.1 ^ permalink raw reply related [flat|nested] 66+ messages in thread
* Re: [RFC PATCH v4 16/19] hw/arm/virt: Replace TARGET_AARCH64 -> target_aarch64() 2025-04-22 14:54 ` [RFC PATCH v4 16/19] hw/arm/virt: Replace TARGET_AARCH64 -> target_aarch64() Philippe Mathieu-Daudé @ 2025-04-22 17:47 ` Richard Henderson 2025-04-22 18:22 ` Pierrick Bouvier 1 sibling, 0 replies; 66+ messages in thread From: Richard Henderson @ 2025-04-22 17:47 UTC (permalink / raw) To: Philippe Mathieu-Daudé, qemu-devel, Pierrick Bouvier; +Cc: Anton Johansson On 4/22/25 07:54, Philippe Mathieu-Daudé wrote: > Replace the target-specific TARGET_AARCH64 definition > by a call to the generic target_aarch64() helper. > > Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org> > --- > This removes the last TARGET_AARCH64 in hw/arm/. > --- > hw/arm/virt.c | 9 +++++---- > 1 file changed, 5 insertions(+), 4 deletions(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~ ^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [RFC PATCH v4 16/19] hw/arm/virt: Replace TARGET_AARCH64 -> target_aarch64() 2025-04-22 14:54 ` [RFC PATCH v4 16/19] hw/arm/virt: Replace TARGET_AARCH64 -> target_aarch64() Philippe Mathieu-Daudé 2025-04-22 17:47 ` Richard Henderson @ 2025-04-22 18:22 ` Pierrick Bouvier 1 sibling, 0 replies; 66+ messages in thread From: Pierrick Bouvier @ 2025-04-22 18:22 UTC (permalink / raw) To: Philippe Mathieu-Daudé, qemu-devel Cc: Richard Henderson, Anton Johansson On 4/22/25 07:54, Philippe Mathieu-Daudé wrote: > Replace the target-specific TARGET_AARCH64 definition > by a call to the generic target_aarch64() helper. > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- > This removes the last TARGET_AARCH64 in hw/arm/. > --- > hw/arm/virt.c | 9 +++++---- > 1 file changed, 5 insertions(+), 4 deletions(-) > > diff --git a/hw/arm/virt.c b/hw/arm/virt.c > index d7197958f7c..4e11272a3ac 100644 > --- a/hw/arm/virt.c > +++ b/hw/arm/virt.c > @@ -32,6 +32,7 @@ > #include "qemu/datadir.h" > #include "qemu/units.h" > #include "qemu/option.h" > +#include "qemu/target-info.h" > #include "monitor/qdev.h" > #include "hw/sysbus.h" > #include "hw/arm/boot.h" > @@ -3137,7 +3138,8 @@ static GSList *virt_get_valid_cpu_types(const MachineState *ms) > if (tcg_enabled()) { > vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a7"))); > vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a15"))); > -#ifdef TARGET_AARCH64 > + } > + if (tcg_enabled() && target_aarch64()) { > vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a35"))); > vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a55"))); > vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a72"))); > @@ -3147,15 +3149,14 @@ static GSList *virt_get_valid_cpu_types(const MachineState *ms) > vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-n1"))); > vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-v1"))); > vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-n2"))); > -#endif /* TARGET_AARCH64 */ > } > -#ifdef TARGET_AARCH64 > + if (target_aarch64()) { > vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a53"))); > vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a57"))); > if (kvm_enabled() || hvf_enabled()) { > vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("host"))); > } > -#endif /* TARGET_AARCH64 */ > + } > vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("max"))); > > return vct; Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> ^ permalink raw reply [flat|nested] 66+ messages in thread
* [RFC PATCH v4 17/19] hw/core: Get default_cpu_type calling machine_class_default_cpu_type() 2025-04-22 14:54 [RFC PATCH v4 00/19] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé ` (15 preceding siblings ...) 2025-04-22 14:54 ` [RFC PATCH v4 16/19] hw/arm/virt: Replace TARGET_AARCH64 -> target_aarch64() Philippe Mathieu-Daudé @ 2025-04-22 14:54 ` Philippe Mathieu-Daudé 2025-04-22 17:58 ` Richard Henderson 2025-04-22 18:23 ` Pierrick Bouvier 2025-04-22 14:55 ` [RFC PATCH v4 18/19] hw/core: Introduce MachineClass::get_default_cpu_type() helper Philippe Mathieu-Daudé 2025-04-22 14:55 ` [RFC PATCH v4 19/19] hw/arm/virt: Get default CPU type at runtime Philippe Mathieu-Daudé 18 siblings, 2 replies; 66+ messages in thread From: Philippe Mathieu-Daudé @ 2025-04-22 14:54 UTC (permalink / raw) To: qemu-devel, Pierrick Bouvier; +Cc: Richard Henderson, Anton Johansson Since commit 62b4a227a33 the default cpu type can come from the valid_cpu_types[] array. Call the machine_class_default_cpu_type() instead of accessing MachineClass::default_cpu_type field. Cc: qemu-stable@nongnu.org Fixes: 62b4a227a33 ("hw/core: Add machine_class_default_cpu_type()") Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- Cc: Gavin Shan <gshan@redhat.com> --- hw/core/machine-qmp-cmds.c | 5 +++-- target/ppc/cpu_init.c | 2 +- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/hw/core/machine-qmp-cmds.c b/hw/core/machine-qmp-cmds.c index 529ce8dd9a0..a8f8f8c8138 100644 --- a/hw/core/machine-qmp-cmds.c +++ b/hw/core/machine-qmp-cmds.c @@ -73,6 +73,7 @@ MachineInfoList *qmp_query_machines(bool has_compat_props, bool compat_props, for (el = machines; el; el = el->next) { MachineClass *mc = el->data; + const char *default_cpu_type = machine_class_default_cpu_type(mc); MachineInfo *info; info = g_malloc0(sizeof(*info)); @@ -91,8 +92,8 @@ MachineInfoList *qmp_query_machines(bool has_compat_props, bool compat_props, info->numa_mem_supported = mc->numa_mem_supported; info->deprecated = !!mc->deprecation_reason; info->acpi = !!object_class_property_find(OBJECT_CLASS(mc), "acpi"); - if (mc->default_cpu_type) { - info->default_cpu_type = g_strdup(mc->default_cpu_type); + if (default_cpu_type) { + info->default_cpu_type = g_strdup(default_cpu_type); } if (mc->default_ram_id) { info->default_ram_id = g_strdup(mc->default_ram_id); diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index a3dff0814d1..2c0db2a05a9 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7081,7 +7081,7 @@ ObjectClass *ppc_cpu_class_by_name(const char *name) if (strcmp(name, "max") == 0) { MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); if (mc) { - return object_class_by_name(mc->default_cpu_type); + return object_class_by_name(machine_class_default_cpu_type(mc)); } } #endif -- 2.47.1 ^ permalink raw reply related [flat|nested] 66+ messages in thread
* Re: [RFC PATCH v4 17/19] hw/core: Get default_cpu_type calling machine_class_default_cpu_type() 2025-04-22 14:54 ` [RFC PATCH v4 17/19] hw/core: Get default_cpu_type calling machine_class_default_cpu_type() Philippe Mathieu-Daudé @ 2025-04-22 17:58 ` Richard Henderson 2025-04-22 18:23 ` Pierrick Bouvier 1 sibling, 0 replies; 66+ messages in thread From: Richard Henderson @ 2025-04-22 17:58 UTC (permalink / raw) To: Philippe Mathieu-Daudé, qemu-devel, Pierrick Bouvier; +Cc: Anton Johansson On 4/22/25 07:54, Philippe Mathieu-Daudé wrote: > Since commit 62b4a227a33 the default cpu type can come from the > valid_cpu_types[] array. Call the machine_class_default_cpu_type() > instead of accessing MachineClass::default_cpu_type field. > > Cc: qemu-stable@nongnu.org > Fixes: 62b4a227a33 ("hw/core: Add machine_class_default_cpu_type()") > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- > Cc: Gavin Shan <gshan@redhat.com> > --- > hw/core/machine-qmp-cmds.c | 5 +++-- > target/ppc/cpu_init.c | 2 +- > 2 files changed, 4 insertions(+), 3 deletions(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~ ^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [RFC PATCH v4 17/19] hw/core: Get default_cpu_type calling machine_class_default_cpu_type() 2025-04-22 14:54 ` [RFC PATCH v4 17/19] hw/core: Get default_cpu_type calling machine_class_default_cpu_type() Philippe Mathieu-Daudé 2025-04-22 17:58 ` Richard Henderson @ 2025-04-22 18:23 ` Pierrick Bouvier 1 sibling, 0 replies; 66+ messages in thread From: Pierrick Bouvier @ 2025-04-22 18:23 UTC (permalink / raw) To: Philippe Mathieu-Daudé, qemu-devel Cc: Richard Henderson, Anton Johansson On 4/22/25 07:54, Philippe Mathieu-Daudé wrote: > Since commit 62b4a227a33 the default cpu type can come from the > valid_cpu_types[] array. Call the machine_class_default_cpu_type() > instead of accessing MachineClass::default_cpu_type field. > > Cc: qemu-stable@nongnu.org > Fixes: 62b4a227a33 ("hw/core: Add machine_class_default_cpu_type()") > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- > Cc: Gavin Shan <gshan@redhat.com> > --- > hw/core/machine-qmp-cmds.c | 5 +++-- > target/ppc/cpu_init.c | 2 +- > 2 files changed, 4 insertions(+), 3 deletions(-) > > diff --git a/hw/core/machine-qmp-cmds.c b/hw/core/machine-qmp-cmds.c > index 529ce8dd9a0..a8f8f8c8138 100644 > --- a/hw/core/machine-qmp-cmds.c > +++ b/hw/core/machine-qmp-cmds.c > @@ -73,6 +73,7 @@ MachineInfoList *qmp_query_machines(bool has_compat_props, bool compat_props, > > for (el = machines; el; el = el->next) { > MachineClass *mc = el->data; > + const char *default_cpu_type = machine_class_default_cpu_type(mc); > MachineInfo *info; > > info = g_malloc0(sizeof(*info)); > @@ -91,8 +92,8 @@ MachineInfoList *qmp_query_machines(bool has_compat_props, bool compat_props, > info->numa_mem_supported = mc->numa_mem_supported; > info->deprecated = !!mc->deprecation_reason; > info->acpi = !!object_class_property_find(OBJECT_CLASS(mc), "acpi"); > - if (mc->default_cpu_type) { > - info->default_cpu_type = g_strdup(mc->default_cpu_type); > + if (default_cpu_type) { > + info->default_cpu_type = g_strdup(default_cpu_type); > } > if (mc->default_ram_id) { > info->default_ram_id = g_strdup(mc->default_ram_id); > diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c > index a3dff0814d1..2c0db2a05a9 100644 > --- a/target/ppc/cpu_init.c > +++ b/target/ppc/cpu_init.c > @@ -7081,7 +7081,7 @@ ObjectClass *ppc_cpu_class_by_name(const char *name) > if (strcmp(name, "max") == 0) { > MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); > if (mc) { > - return object_class_by_name(mc->default_cpu_type); > + return object_class_by_name(machine_class_default_cpu_type(mc)); > } > } > #endif Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> ^ permalink raw reply [flat|nested] 66+ messages in thread
* [RFC PATCH v4 18/19] hw/core: Introduce MachineClass::get_default_cpu_type() helper 2025-04-22 14:54 [RFC PATCH v4 00/19] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé ` (16 preceding siblings ...) 2025-04-22 14:54 ` [RFC PATCH v4 17/19] hw/core: Get default_cpu_type calling machine_class_default_cpu_type() Philippe Mathieu-Daudé @ 2025-04-22 14:55 ` Philippe Mathieu-Daudé 2025-04-22 17:59 ` Richard Henderson 2025-04-22 14:55 ` [RFC PATCH v4 19/19] hw/arm/virt: Get default CPU type at runtime Philippe Mathieu-Daudé 18 siblings, 1 reply; 66+ messages in thread From: Philippe Mathieu-Daudé @ 2025-04-22 14:55 UTC (permalink / raw) To: qemu-devel, Pierrick Bouvier; +Cc: Richard Henderson, Anton Johansson MachineClass::get_default_cpu_type() runs once the machine is created, being able to evaluate runtime checks; it returns the machine default CPU type. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- include/hw/boards.h | 6 ++++++ hw/core/machine.c | 10 ++++++++++ system/vl.c | 2 +- 3 files changed, 17 insertions(+), 1 deletion(-) diff --git a/include/hw/boards.h b/include/hw/boards.h index be0c0f04804..6a0b02db42e 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -25,6 +25,11 @@ OBJECT_DECLARE_TYPE(MachineState, MachineClass, MACHINE) extern MachineState *current_machine; +/** + * machine_default_cpu_type: Return the machine default CPU type. + * @ms: Machine state + */ +const char *machine_default_cpu_type(const MachineState *ms); /** * machine_class_default_cpu_type: Return the machine default CPU type. * @mc: Machine class @@ -310,6 +315,7 @@ struct MachineClass { int numa_mem_align_shift; const char * const *valid_cpu_types; GSList *(*get_valid_cpu_types)(const MachineState *ms); + const char *(*get_default_cpu_type)(const MachineState *ms); strList *allowed_dynamic_sysbus_devices; bool auto_enable_numa_with_memhp; bool auto_enable_numa_with_memdev; diff --git a/hw/core/machine.c b/hw/core/machine.c index 8b40735ef98..89169a2dbae 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -1538,6 +1538,16 @@ const char *machine_class_default_cpu_type(MachineClass *mc) return mc->default_cpu_type; } +const char *machine_default_cpu_type(const MachineState *ms) +{ + MachineClass *mc = MACHINE_GET_CLASS(ms); + + if (mc->get_default_cpu_type) { + return mc->get_default_cpu_type(ms); + } + return machine_class_default_cpu_type(mc); +} + static bool is_cpu_type_supported(const MachineState *machine, Error **errp) { MachineClass *mc = MACHINE_GET_CLASS(machine); diff --git a/system/vl.c b/system/vl.c index e8706a9ce87..338f9d75289 100644 --- a/system/vl.c +++ b/system/vl.c @@ -3825,7 +3825,7 @@ void qemu_init(int argc, char **argv) migration_object_init(); /* parse features once if machine provides default cpu_type */ - current_machine->cpu_type = machine_class_default_cpu_type(machine_class); + current_machine->cpu_type = machine_default_cpu_type(current_machine); if (cpu_option) { current_machine->cpu_type = parse_cpu_option(cpu_option); } -- 2.47.1 ^ permalink raw reply related [flat|nested] 66+ messages in thread
* Re: [RFC PATCH v4 18/19] hw/core: Introduce MachineClass::get_default_cpu_type() helper 2025-04-22 14:55 ` [RFC PATCH v4 18/19] hw/core: Introduce MachineClass::get_default_cpu_type() helper Philippe Mathieu-Daudé @ 2025-04-22 17:59 ` Richard Henderson 2025-04-22 18:24 ` Pierrick Bouvier 0 siblings, 1 reply; 66+ messages in thread From: Richard Henderson @ 2025-04-22 17:59 UTC (permalink / raw) To: Philippe Mathieu-Daudé, qemu-devel, Pierrick Bouvier; +Cc: Anton Johansson On 4/22/25 07:55, Philippe Mathieu-Daudé wrote: > MachineClass::get_default_cpu_type() runs once the machine is > created, being able to evaluate runtime checks; it returns the > machine default CPU type. > > Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org> > --- > include/hw/boards.h | 6 ++++++ > hw/core/machine.c | 10 ++++++++++ > system/vl.c | 2 +- > 3 files changed, 17 insertions(+), 1 deletion(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~ ^ permalink raw reply [flat|nested] 66+ messages in thread
* Re: [RFC PATCH v4 18/19] hw/core: Introduce MachineClass::get_default_cpu_type() helper 2025-04-22 17:59 ` Richard Henderson @ 2025-04-22 18:24 ` Pierrick Bouvier 0 siblings, 0 replies; 66+ messages in thread From: Pierrick Bouvier @ 2025-04-22 18:24 UTC (permalink / raw) To: Richard Henderson, Philippe Mathieu-Daudé, qemu-devel Cc: Anton Johansson On 4/22/25 10:59, Richard Henderson wrote: > On 4/22/25 07:55, Philippe Mathieu-Daudé wrote: >> MachineClass::get_default_cpu_type() runs once the machine is >> created, being able to evaluate runtime checks; it returns the >> machine default CPU type. >> >> Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org> >> --- >> include/hw/boards.h | 6 ++++++ >> hw/core/machine.c | 10 ++++++++++ >> system/vl.c | 2 +- >> 3 files changed, 17 insertions(+), 1 deletion(-) > > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > > r~ Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> ^ permalink raw reply [flat|nested] 66+ messages in thread
* [RFC PATCH v4 19/19] hw/arm/virt: Get default CPU type at runtime 2025-04-22 14:54 [RFC PATCH v4 00/19] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé ` (17 preceding siblings ...) 2025-04-22 14:55 ` [RFC PATCH v4 18/19] hw/core: Introduce MachineClass::get_default_cpu_type() helper Philippe Mathieu-Daudé @ 2025-04-22 14:55 ` Philippe Mathieu-Daudé 2025-04-22 18:06 ` Richard Henderson 18 siblings, 1 reply; 66+ messages in thread From: Philippe Mathieu-Daudé @ 2025-04-22 14:55 UTC (permalink / raw) To: qemu-devel, Pierrick Bouvier; +Cc: Richard Henderson, Anton Johansson Prefer MachineClass::get_default_cpu_type() over MachineClass::default_cpu_type to get CPU type, evaluating TCG availability at runtime calling tcg_enabled(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- This removes the last use of CONFIG_TCG in hw/arm/. --- hw/arm/virt.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 4e11272a3ac..df8dda812cc 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -3131,6 +3131,12 @@ static int virt_hvf_get_physical_address_range(MachineState *ms) return requested_ipa_size; } +static const char *virt_get_default_cpu_type(const MachineState *ms) +{ + return tcg_enabled() ? ARM_CPU_TYPE_NAME("cortex-a15") + : ARM_CPU_TYPE_NAME("max"); +} + static GSList *virt_get_valid_cpu_types(const MachineState *ms) { GSList *vct = NULL; @@ -3188,11 +3194,7 @@ static void virt_machine_class_init(ObjectClass *oc, void *data) mc->minimum_page_bits = 12; mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; mc->cpu_index_to_instance_props = virt_cpu_index_to_props; -#ifdef CONFIG_TCG - mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); -#else - mc->default_cpu_type = ARM_CPU_TYPE_NAME("max"); -#endif + mc->get_default_cpu_type = virt_get_default_cpu_type; mc->get_valid_cpu_types = virt_get_valid_cpu_types; mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; mc->kvm_type = virt_kvm_type; -- 2.47.1 ^ permalink raw reply related [flat|nested] 66+ messages in thread
* Re: [RFC PATCH v4 19/19] hw/arm/virt: Get default CPU type at runtime 2025-04-22 14:55 ` [RFC PATCH v4 19/19] hw/arm/virt: Get default CPU type at runtime Philippe Mathieu-Daudé @ 2025-04-22 18:06 ` Richard Henderson 0 siblings, 0 replies; 66+ messages in thread From: Richard Henderson @ 2025-04-22 18:06 UTC (permalink / raw) To: Philippe Mathieu-Daudé, qemu-devel, Pierrick Bouvier; +Cc: Anton Johansson On 4/22/25 07:55, Philippe Mathieu-Daudé wrote: > Prefer MachineClass::get_default_cpu_type() over > MachineClass::default_cpu_type to get CPU type, > evaluating TCG availability at runtime calling > tcg_enabled(). > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- > This removes the last use of CONFIG_TCG in hw/arm/. > --- > hw/arm/virt.c | 12 +++++++----- > 1 file changed, 7 insertions(+), 5 deletions(-) > > diff --git a/hw/arm/virt.c b/hw/arm/virt.c > index 4e11272a3ac..df8dda812cc 100644 > --- a/hw/arm/virt.c > +++ b/hw/arm/virt.c > @@ -3131,6 +3131,12 @@ static int virt_hvf_get_physical_address_range(MachineState *ms) > return requested_ipa_size; > } > > +static const char *virt_get_default_cpu_type(const MachineState *ms) > +{ > + return tcg_enabled() ? ARM_CPU_TYPE_NAME("cortex-a15") > + : ARM_CPU_TYPE_NAME("max"); > +} > + > static GSList *virt_get_valid_cpu_types(const MachineState *ms) > { > GSList *vct = NULL; > @@ -3188,11 +3194,7 @@ static void virt_machine_class_init(ObjectClass *oc, void *data) > mc->minimum_page_bits = 12; > mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; > mc->cpu_index_to_instance_props = virt_cpu_index_to_props; > -#ifdef CONFIG_TCG > - mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); > -#else > - mc->default_cpu_type = ARM_CPU_TYPE_NAME("max"); > -#endif > + mc->get_default_cpu_type = virt_get_default_cpu_type; It's worth noting that this is a behavior change. Previously only ./configure --disable-tcg --enable-kvm ./qemu-system-aarch64 -M virt -accel kvm would default to 'max' and ./configure --enable-tcg --enable-kvm ./qemu-system-aarch64 -M virt -accel kvm would default to 'cortex-a15'. Afterward, -accel kvm will always default to 'max'. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~ ^ permalink raw reply [flat|nested] 66+ messages in thread
end of thread, other threads:[~2025-04-23 20:12 UTC | newest] Thread overview: 66+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-04-22 14:54 [RFC PATCH v4 00/19] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé 2025-04-22 14:54 ` [RFC PATCH v4 01/19] qapi: Rename TargetInfo structure as QemuTargetInfo Philippe Mathieu-Daudé 2025-04-22 14:57 ` Philippe Mathieu-Daudé 2025-04-22 17:33 ` Markus Armbruster 2025-04-22 14:54 ` [RFC PATCH v4 02/19] qemu: Convert target_name() to TargetInfo API Philippe Mathieu-Daudé 2025-04-22 17:27 ` Richard Henderson 2025-04-22 17:28 ` Richard Henderson 2025-04-22 14:54 ` [RFC PATCH v4 03/19] system/vl: Filter machine list available for a particular target binary Philippe Mathieu-Daudé 2025-04-22 17:29 ` Richard Henderson 2025-04-22 14:54 ` [RFC PATCH v4 04/19] hw/arm: Register TYPE_TARGET_ARM/AARCH64_MACHINE QOM interfaces Philippe Mathieu-Daudé 2025-04-22 17:31 ` Richard Henderson 2025-04-22 14:54 ` [RFC PATCH v4 05/19] hw/core: Allow ARM/Aarch64 binaries to use the 'none' machine Philippe Mathieu-Daudé 2025-04-22 17:34 ` Richard Henderson 2025-04-22 14:54 ` [RFC PATCH v4 06/19] hw/arm: Filter machine types for qemu-system-arm/aarch64 binaries Philippe Mathieu-Daudé 2025-04-22 17:40 ` Richard Henderson 2025-04-23 16:34 ` Philippe Mathieu-Daudé 2025-04-23 17:43 ` Pierrick Bouvier 2025-04-23 19:12 ` Richard Henderson 2025-04-23 19:33 ` Pierrick Bouvier 2025-04-23 19:53 ` Philippe Mathieu-Daudé 2025-04-23 20:10 ` Pierrick Bouvier 2025-04-23 20:04 ` Richard Henderson 2025-04-23 20:12 ` Pierrick Bouvier 2025-04-23 17:07 ` Philippe Mathieu-Daudé 2025-04-22 14:54 ` [RFC PATCH v4 07/19] meson: Prepare to accept per-binary TargetInfo structure implementation Philippe Mathieu-Daudé 2025-04-22 17:41 ` Richard Henderson 2025-04-22 14:54 ` [RFC PATCH v4 08/19] config/target: Implement per-binary TargetInfo structure (ARM, AARCH64) Philippe Mathieu-Daudé 2025-04-22 17:42 ` Richard Henderson 2025-04-22 14:54 ` [RFC PATCH v4 09/19] hw/arm/aspeed: Build objects once Philippe Mathieu-Daudé 2025-04-22 17:42 ` Richard Henderson 2025-04-22 14:54 ` [RFC PATCH v4 10/19] hw/arm/raspi: " Philippe Mathieu-Daudé 2025-04-22 17:43 ` Richard Henderson 2025-04-22 14:54 ` [RFC PATCH v4 11/19] hw/core/machine: Allow dynamic registration of valid CPU types Philippe Mathieu-Daudé 2025-04-22 17:54 ` Richard Henderson 2025-04-22 18:06 ` Pierrick Bouvier 2025-04-22 14:54 ` [RFC PATCH v4 12/19] hw/arm/virt: Register valid CPU types dynamically Philippe Mathieu-Daudé 2025-04-22 17:56 ` Richard Henderson 2025-04-22 18:10 ` Pierrick Bouvier 2025-04-22 18:18 ` Philippe Mathieu-Daudé 2025-04-22 14:54 ` [RFC PATCH v4 13/19] hw/arm/virt: Check accelerator availability at runtime Philippe Mathieu-Daudé 2025-04-22 17:56 ` Richard Henderson 2025-04-22 18:18 ` Pierrick Bouvier 2025-04-22 14:54 ` [RFC PATCH v4 14/19] qemu/target_info: Add %target_arch field to TargetInfo Philippe Mathieu-Daudé 2025-04-22 17:46 ` Richard Henderson 2025-04-22 18:20 ` Pierrick Bouvier 2025-04-22 18:24 ` Philippe Mathieu-Daudé 2025-04-22 18:30 ` Pierrick Bouvier 2025-04-23 5:34 ` Philippe Mathieu-Daudé 2025-04-23 6:24 ` Pierrick Bouvier 2025-04-23 6:28 ` Pierrick Bouvier 2025-04-23 9:14 ` Philippe Mathieu-Daudé 2025-04-23 14:59 ` Pierrick Bouvier 2025-04-22 14:54 ` [RFC PATCH v4 15/19] qemu/target_info: Add target_aarch64() helper Philippe Mathieu-Daudé 2025-04-22 17:46 ` Richard Henderson 2025-04-22 18:21 ` Pierrick Bouvier 2025-04-22 14:54 ` [RFC PATCH v4 16/19] hw/arm/virt: Replace TARGET_AARCH64 -> target_aarch64() Philippe Mathieu-Daudé 2025-04-22 17:47 ` Richard Henderson 2025-04-22 18:22 ` Pierrick Bouvier 2025-04-22 14:54 ` [RFC PATCH v4 17/19] hw/core: Get default_cpu_type calling machine_class_default_cpu_type() Philippe Mathieu-Daudé 2025-04-22 17:58 ` Richard Henderson 2025-04-22 18:23 ` Pierrick Bouvier 2025-04-22 14:55 ` [RFC PATCH v4 18/19] hw/core: Introduce MachineClass::get_default_cpu_type() helper Philippe Mathieu-Daudé 2025-04-22 17:59 ` Richard Henderson 2025-04-22 18:24 ` Pierrick Bouvier 2025-04-22 14:55 ` [RFC PATCH v4 19/19] hw/arm/virt: Get default CPU type at runtime Philippe Mathieu-Daudé 2025-04-22 18:06 ` Richard Henderson
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