From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Hk4U5-0004JF-Ku for qemu-devel@nongnu.org; Fri, 04 May 2007 16:34:33 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Hk4U4-0004IU-6g for qemu-devel@nongnu.org; Fri, 04 May 2007 16:34:33 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Hk4U3-0004IL-G9 for qemu-devel@nongnu.org; Fri, 04 May 2007 16:34:31 -0400 Received: from wr-out-0506.google.com ([64.233.184.235]) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1Hk4NN-0007tw-Er for qemu-devel@nongnu.org; Fri, 04 May 2007 16:27:37 -0400 Received: by wr-out-0506.google.com with SMTP id i20so1927061wra for ; Fri, 04 May 2007 13:27:35 -0700 (PDT) Message-ID: Date: Fri, 4 May 2007 23:27:33 +0300 From: "Blue Swirl" Subject: Re: [Qemu-devel] [BUG] QEMU crash during cpu reset (MIPS regression) In-Reply-To: <463B939A.1090508@mail.berlios.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Content-Disposition: inline References: <463B939A.1090508@mail.berlios.de> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org On 5/4/07, Stefan Weil wrote: > Resetting a MIPS cpu currently does not work, because important > entries in env (CPUMIPSState) are filled with 0 at the > beginning of function cpu_reset. > > At system start, these values are set in cpu_mips_register. > > After reset, env->nb_tlb == 0 results in a division by zero > crash of QEMU. > > We can either re-arrange the entries in CPUMIPSState > (move those which must not be zero'ed to the end), or > cpu_reset must call cpu_mips_register. > > Which solution is better? I solved the same issue on Sparc side by not zeroing most of the state. This is in line with the real Sparc hardware.