From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1HypsL-0005A2-Eh for qemu-devel@nongnu.org; Thu, 14 Jun 2007 10:00:37 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1HypsI-000592-Tr for qemu-devel@nongnu.org; Thu, 14 Jun 2007 10:00:37 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1HypsI-00058x-Lk for qemu-devel@nongnu.org; Thu, 14 Jun 2007 10:00:34 -0400 Received: from wr-out-0506.google.com ([64.233.184.224]) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1HypsI-00046x-5y for qemu-devel@nongnu.org; Thu, 14 Jun 2007 10:00:34 -0400 Received: by wr-out-0506.google.com with SMTP id 71so962950wri for ; Thu, 14 Jun 2007 07:00:33 -0700 (PDT) Message-ID: Date: Thu, 14 Jun 2007 17:00:32 +0300 From: "Blue Swirl" Subject: Re: [Qemu-devel] CPUTLBEntry Question In-Reply-To: <20070614134136.GA6825@163.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Content-Disposition: inline References: <812074ac0706131325t578dfd5eiaa5836b160a24679@mail.gmail.com> <20070614134136.GA6825@163.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: amateur , qemu-devel@nongnu.org On 6/14/07, amateur wrote: > The softmmu_header.h code does assume each TLB entry has a fixed size > of (2^CPU_TLB_ENTRY_BITS) bytes. Not only the assembly code, but also > the C code assume this. So if you want to add new members into > CPUTLBEntry, add the new member at the end of the data structure, and > adjust CPU_TLB_ENTRY_BITS accordingly. No, on Sparc32 target_ulong is 32 bits (on 32-bit host) but target_phys_addr_t is 64 bits. That makes the structure size 20 bytes. Everything still works.