From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1IYoyU-0006Ng-MF for qemu-devel@nongnu.org; Fri, 21 Sep 2007 16:19:42 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1IYoyQ-0006Kb-Si for qemu-devel@nongnu.org; Fri, 21 Sep 2007 16:19:42 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1IYoyQ-0006KB-Jw for qemu-devel@nongnu.org; Fri, 21 Sep 2007 16:19:38 -0400 Received: from nf-out-0910.google.com ([64.233.182.187]) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1IYoyQ-0007ix-1T for qemu-devel@nongnu.org; Fri, 21 Sep 2007 16:19:38 -0400 Received: by nf-out-0910.google.com with SMTP id 30so902892nfu for ; Fri, 21 Sep 2007 13:19:37 -0700 (PDT) Message-ID: Date: Fri, 21 Sep 2007 23:19:36 +0300 From: "Blue Swirl" Subject: Re: [Qemu-devel] sparc32 counter/timer issues In-Reply-To: <46F3D3A1.1040300@earthlink.net> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="----=_Part_41500_16360959.1190405976575" References: <46F3D3A1.1040300@earthlink.net> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org ------=_Part_41500_16360959.1190405976575 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Content-Disposition: inline On 9/21/07, Robert Reif wrote: > I'm trying to run a real ss10 openboot prom image rather than > the supplied prom image and found some issues with the way > counters and timers are implemented. It appears that the processor > and system counter/timers are not independent. The system > config register actually configures the processor counter/timers > and the config register is actually a bit mask of the counter/timer > to configure. 1, 2, 4, and 8 are used to as config values for each > processor counter/timer and 0xf is used for setting all of them. > This isn't apparent in the slaveio documentation because it is > for a single cpu only. > > Because the system config register configures the processor > timers, it needs access to all the processor timers (or the > processor timers need access to the system timer). This isn't > how it's currently implemented. Thanks for testing. This patch changes the config register to what you described, everything seems to work like before. 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