Re: [Qemu-devel] RFC: Code fetch optimisation

["Blue Swirl" <blauwirbel@gmail.com>]

On 10/12/07, J. Mayer <l_indien@magic.fr> wrote:
> Here's a small patch that allow an optimisation for code fetch, at least
> for RISC CPU targets, as suggested by Fabrice Bellard.
> The main idea is that a translated block is never to span over a page
> boundary. As the tb_find_slow routine already gets the physical address
> of the page of code to be translated, the code translator could then
> fetch the code using raw host memory accesses instead of doing it
> through the softmmu routines.
> This patch could also be adapted to RISC CPU targets, with care for the
> last instruction of a page. For now, I did implement it for alpha, arm,
> mips, PowerPC and SH4.
> I don't actually know if the optimsation would bring a sensible speed
> gain or if it will be absolutelly marginal.
>
> Please comment.

This will not work correctly for execution of MMIO registers, but
maybe that won't work on real hardware either. Who cares.

Wouldn't it be even more efficient if you moved most of this calculation:
+    phys_pc = (unsigned long)phys_ram_base + tb->page_addr[0] +
+        (pc_start & ~TARGET_PAGE_MASK);
here:
+    tb->page_addr[0] = phys_page1;
?