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From: "Blue Swirl" <blauwirbel@gmail.com>
To: qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [RFC] sparc32 MXCC support
Date: Sun, 14 Oct 2007 10:37:14 +0300	[thread overview]
Message-ID: <f43fc5580710140037w20385f58le158acde8df81884@mail.gmail.com> (raw)
In-Reply-To: <47112DFE.4050600@earthlink.net>

On 10/13/07, Robert Reif <reif@earthlink.net> wrote:
> I'm trying to add SuperSparc II MXCC support and need some feedback.
>
> Is there a better way to read and write physical memory in 64bit chunks?
> I'm not sure what I'm doing is portable between 32/64 and big/little endian.

Thank you for your effort. Applying the patch allows NetBSD on SS-10
to boot as far as on SS-5, previously it crashed.

I think the code is portable, but I think changing the register type
to uint32_t and using a DPRINTF system like used in for example
hw/iommu.c should make the code slightly clearer.

For the memory access, ldl/q_phys/stl/q_phys is used in other block
copy routines. For longer blocks or if the address can be unaligned,
cpu_physical_memory_read() could be a better choice.

> +int cpu_sparc_register (CPUSPARCState *env, const sparc_def_t *def, int cpu);

unsigned int cpu?

> +                printf("ERROR: helper_ld_asi(asi = %d, size = %d, sign = %d) T0 = %08x: unsupported size\n", asi, size, sign, T0);

If it's an error to access the registers with different size, you
should use do_unassigned_access() to report this.

  reply	other threads:[~2007-10-14  7:37 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2007-10-13 20:43 [Qemu-devel] [RFC] sparc32 MXCC support Robert Reif
2007-10-14  7:37 ` Blue Swirl [this message]
2007-10-14 13:36   ` Robert Reif

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