From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43)
	id 1Igy2J-0008Py-3s
	for qemu-devel@nongnu.org; Sun, 14 Oct 2007 03:37:19 -0400
Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43)
	id 1Igy2H-0008MH-Dy
	for qemu-devel@nongnu.org; Sun, 14 Oct 2007 03:37:18 -0400
Received: from [199.232.76.173] (helo=monty-python.gnu.org)
	by lists.gnu.org with esmtp (Exim 4.43) id 1Igy2H-0008Lx-9N
	for qemu-devel@nongnu.org; Sun, 14 Oct 2007 03:37:17 -0400
Received: from mu-out-0910.google.com ([209.85.134.191])
	by monty-python.gnu.org with esmtp (Exim 4.60)
	(envelope-from <blauwirbel@gmail.com>) id 1Igy2G-00009i-VY
	for qemu-devel@nongnu.org; Sun, 14 Oct 2007 03:37:17 -0400
Received: by mu-out-0910.google.com with SMTP id w8so1207537mue
	for <qemu-devel@nongnu.org>; Sun, 14 Oct 2007 00:37:14 -0700 (PDT)
Message-ID: <f43fc5580710140037w20385f58le158acde8df81884@mail.gmail.com>
Date: Sun, 14 Oct 2007 10:37:14 +0300
From: "Blue Swirl" <blauwirbel@gmail.com>
Subject: Re: [Qemu-devel] [RFC] sparc32 MXCC support
In-Reply-To: <47112DFE.4050600@earthlink.net>
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 7bit
Content-Disposition: inline
References: <47112DFE.4050600@earthlink.net>
Reply-To: qemu-devel@nongnu.org
List-Id: qemu-devel.nongnu.org
List-Unsubscribe: <http://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.gnu.org/pipermail/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <http://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: qemu-devel@nongnu.org

On 10/13/07, Robert Reif <reif@earthlink.net> wrote:
> I'm trying to add SuperSparc II MXCC support and need some feedback.
>
> Is there a better way to read and write physical memory in 64bit chunks?
> I'm not sure what I'm doing is portable between 32/64 and big/little endian.

Thank you for your effort. Applying the patch allows NetBSD on SS-10
to boot as far as on SS-5, previously it crashed.

I think the code is portable, but I think changing the register type
to uint32_t and using a DPRINTF system like used in for example
hw/iommu.c should make the code slightly clearer.

For the memory access, ldl/q_phys/stl/q_phys is used in other block
copy routines. For longer blocks or if the address can be unaligned,
cpu_physical_memory_read() could be a better choice.

> +int cpu_sparc_register (CPUSPARCState *env, const sparc_def_t *def, int cpu);

unsigned int cpu?

> +                printf("ERROR: helper_ld_asi(asi = %d, size = %d, sign = %d) T0 = %08x: unsupported size\n", asi, size, sign, T0);

If it's an error to access the registers with different size, you
should use do_unassigned_access() to report this.