From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Ih95c-0004Xt-I5 for qemu-devel@nongnu.org; Sun, 14 Oct 2007 15:25:28 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Ih95a-0004XE-LR for qemu-devel@nongnu.org; Sun, 14 Oct 2007 15:25:27 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Ih95a-0004X9-8L for qemu-devel@nongnu.org; Sun, 14 Oct 2007 15:25:26 -0400 Received: from nf-out-0910.google.com ([64.233.182.189]) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1Ih95a-0005gZ-76 for qemu-devel@nongnu.org; Sun, 14 Oct 2007 15:25:26 -0400 Received: by nf-out-0910.google.com with SMTP id 30so1219581nfu for ; Sun, 14 Oct 2007 12:25:25 -0700 (PDT) Message-ID: Date: Sun, 14 Oct 2007 22:25:24 +0300 From: "Blue Swirl" Subject: Re: [Qemu-devel] [PATCH] sparc32 use stq_* for 64bit stores In-Reply-To: <4712614B.9050908@earthlink.net> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Content-Disposition: inline References: <4712614B.9050908@earthlink.net> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org On 10/14/07, Robert Reif wrote: > Use stq_* for 64 bit stores. This could be less optimal for 32 bit hosts, but hopefully the compiler knows its business. > This fixes one bug where T1 was used twice rather than T1 and T2. Great! > Should the address be 64 bit alligned? i.e. T0 & ~7 rather than T0 & ~3? > > Should these unaligned address cause traps? Yes, but the checks are already generated from translate.c (gen_op_check_align_T0_7).