From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1IoZem-00040u-6q for qemu-devel@nongnu.org; Sun, 04 Nov 2007 02:12:28 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1IoZei-0003zi-N5 for qemu-devel@nongnu.org; Sun, 04 Nov 2007 02:12:26 -0500 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1IoZei-0003zf-IV for qemu-devel@nongnu.org; Sun, 04 Nov 2007 02:12:24 -0500 Received: from mx20.gnu.org ([199.232.41.8]) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1IoZeh-0005xv-OY for qemu-devel@nongnu.org; Sun, 04 Nov 2007 02:12:23 -0500 Received: from nf-out-0910.google.com ([64.233.182.188]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1IoZeg-0002LU-A9 for qemu-devel@nongnu.org; Sun, 04 Nov 2007 02:12:22 -0500 Received: by nf-out-0910.google.com with SMTP id 30so1025922nfu for ; Sun, 04 Nov 2007 00:12:20 -0700 (PDT) Message-ID: Date: Sun, 4 Nov 2007 09:12:19 +0200 From: "Blue Swirl" Subject: Re: [Qemu-devel] [PATCH, RFC] Disable implicit self-modifying code support for RISC CPUs In-Reply-To: <472CF299.9000104@bellard.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Content-Disposition: inline References: <472CF299.9000104@bellard.org> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org On 11/4/07, Fabrice Bellard wrote: > Blue Swirl wrote: > > Hi, > > > > RISC CPUs don't support self-modifying code unless the affected area > > is flushed explicitly. This patch disables the extra effort for SMC. > > The changes in this version would affect all CPUs except x86, but I'd > > like to see if there are problems with some target, so that the > > committed change can be limited. Without comments, I'll just disable > > SMC for Sparc, as there are no problems. So please comment, especially > > if you want to "opt in". > > > > For some reason, I can't disable all TB/TLB flushing, for example > > there was already one line with TARGET_HAS_SMC || 1, but removing the > > || 1 part causes crashing. Does anyone know why? > > With the current QEMU architecture, you cannot disable self-modifying > code as you did. This is why I did not fully supported the > TARGET_HAS_SMC flag. The problem is that the translator make the > assumption that the RAM and the TB contents are consistent for example > when handling exceptions. Suppressing this assumption is possible but > requires more work. I think the conclusion is that we would need some kind of emulator for i-cache for any accurate emulation. And handling the boot loader may need an uncached mode. The performance benefit from disabling SMC is unnoticeable according to my benchmarks. Adding a TB flush to i-cache flushing made things worse. Moreover, SMC is hardly ever used on Sparc. I'll just commit the debug statement fixes and the fix that separates PAGE_READ from PAGE_EXEC for Sparc. Maybe this issue should be documented in qemu-tech.texi, there are also frequently some questions about caches.