Re: [Qemu-devel] How to split vl.h

["Blue Swirl" <blauwirbel@gmail.com>]

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On 11/1/07, Fabrice Bellard <fabrice@bellard.org> wrote:
> Blue Swirl wrote:
> > Hi,
> >
> > With the automatic dependency rule installed, modifying vl.h causes
> > all files to be recompiled. This is of course the correct action, but
> > it's a major slowdown for development too.
>
> There must be an option in the Makefile to disable the automatic
> dependency check.
>
> > How should we split vl.h into smaller pieces? Give each device a
> > header file, like m48t59? What about other stuff exported from vl.c?
>
> The net result is that you will have dozens of header files with only
> one line in them as most devices only export one function.

I have another solution: include all architecture specific files from
the main file. This actually makes the compilation faster and the
resulting binary is smaller (maybe faster). Changing the architecture
specific code needs no changes to vl.h, just a recompile of sun4m.c,
but this is instantaneous on my machine. Automatic dependencies also
handle this case. I guess some may find this style pretty ugly.

Similar approach could be taken with the network adapters, sound
cards, Slirp (for the speed, not vl.h effect) etc. by introducing .c
files that include all the others.

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Index: qemu/Makefile.target
===================================================================
--- qemu.orig/Makefile.target	2007-11-04 08:17:00.000000000 +0000
+++ qemu/Makefile.target	2007-11-04 08:20:41.000000000 +0000
@@ -505,9 +505,7 @@
 VL_OBJS+= fdc.o mc146818rtc.o serial.o m48t59.o
 VL_OBJS+= cirrus_vga.o parallel.o ptimer.o
 else
-VL_OBJS+= sun4m.o tcx.o pcnet.o iommu.o m48t59.o slavio_intctl.o
-VL_OBJS+= slavio_timer.o slavio_serial.o slavio_misc.o fdc.o esp.o sparc32_dma.o
-VL_OBJS+= cs4231.o ptimer.o
+VL_OBJS+= sun4m.o
 endif
 endif
 ifeq ($(TARGET_BASE_ARCH), arm)
Index: qemu/hw/cs4231.c
===================================================================
--- qemu.orig/hw/cs4231.c	2007-11-04 08:17:00.000000000 +0000
+++ qemu/hw/cs4231.c	2007-11-04 08:20:41.000000000 +0000
@@ -164,7 +164,7 @@
     return 0;
 }
 
-void cs_init(target_phys_addr_t base, int irq, void *intctl)
+static void cs_init(target_phys_addr_t base, int irq, void *intctl)
 {
     int cs_io_memory;
     CSState *s;
Index: qemu/hw/esp.c
===================================================================
--- qemu.orig/hw/esp.c	2007-11-04 08:17:00.000000000 +0000
+++ qemu/hw/esp.c	2007-11-04 08:20:41.000000000 +0000
@@ -551,7 +551,7 @@
     return 0;
 }
 
-void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id)
+static void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id)
 {
     ESPState *s = (ESPState *)opaque;
 
@@ -574,8 +574,8 @@
     s->scsi_dev[id] = scsi_disk_init(bd, 0, esp_command_complete, s);
 }
 
-void *esp_init(BlockDriverState **bd, target_phys_addr_t espaddr,
-               void *dma_opaque, qemu_irq irq, qemu_irq *reset)
+static void *esp_init(BlockDriverState **bd, target_phys_addr_t espaddr,
+                      void *dma_opaque, qemu_irq irq, qemu_irq *reset)
 {
     ESPState *s;
     int esp_io_memory;
Index: qemu/hw/iommu.c
===================================================================
--- qemu.orig/hw/iommu.c	2007-11-04 08:17:00.000000000 +0000
+++ qemu/hw/iommu.c	2007-11-04 08:20:41.000000000 +0000
@@ -244,8 +244,8 @@
     s->regs[IOMMU_AFAR] = addr;
 }
 
-void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
-                           uint8_t *buf, int len, int is_write)
+static void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
+                                  uint8_t *buf, int len, int is_write)
 {
     int l;
     uint32_t flags;
@@ -311,7 +311,7 @@
     s->regs[IOMMU_CTRL] = IOMMU_VERSION;
 }
 
-void *iommu_init(target_phys_addr_t addr)
+static void *iommu_init(target_phys_addr_t addr)
 {
     IOMMUState *s;
     int iommu_io_memory;
Index: qemu/hw/slavio_intctl.c
===================================================================
--- qemu.orig/hw/slavio_intctl.c	2007-11-04 08:17:00.000000000 +0000
+++ qemu/hw/slavio_intctl.c	2007-11-04 08:20:41.000000000 +0000
@@ -201,7 +201,7 @@
     slavio_intctlm_mem_writel,
 };
 
-void slavio_pic_info(void *opaque)
+static void slavio_pic_info(void *opaque)
 {
     SLAVIO_INTCTLState *s = opaque;
     int i;
@@ -212,7 +212,7 @@
     term_printf("master: pending 0x%08x, disabled 0x%08x\n", s->intregm_pending, s->intregm_disabled);
 }
 
-void slavio_irq_info(void *opaque)
+static void slavio_irq_info(void *opaque)
 {
 #ifndef DEBUG_IRQ_COUNT
     term_printf("irq statistic code not compiled.\n");
@@ -349,10 +349,11 @@
     slavio_check_interrupts(s);
 }
 
-void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
-                         const uint32_t *intbit_to_level,
-                         qemu_irq **irq, qemu_irq **cpu_irq,
-                         qemu_irq **parent_irq, unsigned int cputimer)
+static void *slavio_intctl_init(target_phys_addr_t addr,
+                                target_phys_addr_t addrg,
+                                const uint32_t *intbit_to_level,
+                                qemu_irq **irq, qemu_irq **cpu_irq,
+                                qemu_irq **parent_irq, unsigned int cputimer)
 {
     int slavio_intctl_io_memory, slavio_intctlm_io_memory, i;
     SLAVIO_INTCTLState *s;
Index: qemu/hw/slavio_misc.c
===================================================================
--- qemu.orig/hw/slavio_misc.c	2007-11-04 08:17:00.000000000 +0000
+++ qemu/hw/slavio_misc.c	2007-11-04 08:20:41.000000000 +0000
@@ -70,7 +70,7 @@
     s->config = s->aux1 = s->aux2 = s->mctrl = 0;
 }
 
-void slavio_set_power_fail(void *opaque, int power_failing)
+static void slavio_set_power_fail(void *opaque, int power_failing)
 {
     MiscState *s = opaque;
 
@@ -212,8 +212,9 @@
     return 0;
 }
 
-void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
-                       qemu_irq irq)
+static void *slavio_misc_init(target_phys_addr_t base,
+                              target_phys_addr_t power_base,
+                              qemu_irq irq)
 {
     int slavio_misc_io_memory;
     MiscState *s;
Index: qemu/hw/slavio_serial.c
===================================================================
--- qemu.orig/hw/slavio_serial.c	2007-11-04 08:17:00.000000000 +0000
+++ qemu/hw/slavio_serial.c	2007-11-04 08:20:41.000000000 +0000
@@ -590,8 +590,9 @@
 
 }
 
-SerialState *slavio_serial_init(target_phys_addr_t base, qemu_irq irq,
-                                CharDriverState *chr1, CharDriverState *chr2)
+static SerialState *slavio_serial_init(target_phys_addr_t base, qemu_irq irq,
+                                       CharDriverState *chr1,
+                                       CharDriverState *chr2)
 {
     int slavio_serial_io_memory, i;
     SerialState *s;
@@ -759,7 +760,7 @@
     put_queue(s, 0);
 }
 
-void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq)
+static void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq)
 {
     int slavio_serial_io_memory, i;
     SerialState *s;
Index: qemu/hw/slavio_timer.c
===================================================================
--- qemu.orig/hw/slavio_timer.c	2007-11-04 08:17:00.000000000 +0000
+++ qemu/hw/slavio_timer.c	2007-11-04 08:20:41.000000000 +0000
@@ -325,8 +325,8 @@
     return s;
 }
 
-void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq,
-                           qemu_irq *cpu_irqs)
+static void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq,
+                                  qemu_irq *cpu_irqs)
 {
     SLAVIO_TIMERState *master;
     unsigned int i;
Index: qemu/hw/sparc32_dma.c
===================================================================
--- qemu.orig/hw/sparc32_dma.c	2007-11-04 08:17:00.000000000 +0000
+++ qemu/hw/sparc32_dma.c	2007-11-04 08:20:41.000000000 +0000
@@ -128,7 +128,7 @@
     }
 }
 
-void espdma_memory_read(void *opaque, uint8_t *buf, int len)
+static void espdma_memory_read(void *opaque, uint8_t *buf, int len)
 {
     DMAState *s = opaque;
 
@@ -139,7 +139,7 @@
     s->dmaregs[1] += len;
 }
 
-void espdma_memory_write(void *opaque, uint8_t *buf, int len)
+static void espdma_memory_write(void *opaque, uint8_t *buf, int len)
 {
     DMAState *s = opaque;
 
@@ -237,7 +237,7 @@
     return 0;
 }
 
-void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
+static void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
                        void *iommu, qemu_irq **dev_irq, qemu_irq **reset)
 {
     DMAState *s;
Index: qemu/hw/sun4m.c
===================================================================
--- qemu.orig/hw/sun4m.c	2007-11-04 08:17:00.000000000 +0000
+++ qemu/hw/sun4m.c	2007-11-04 08:20:41.000000000 +0000
@@ -22,6 +22,40 @@
  * THE SOFTWARE.
  */
 #include "vl.h"
+/* iommu.c */
+static void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
+                                  uint8_t *buf, int len, int is_write);
+static inline void sparc_iommu_memory_read(void *opaque,
+                                           target_phys_addr_t addr,
+                                           uint8_t *buf, int len)
+{
+    sparc_iommu_memory_rw(opaque, addr, buf, len, 0);
+}
+
+static inline void sparc_iommu_memory_write(void *opaque,
+                                            target_phys_addr_t addr,
+                                            uint8_t *buf, int len)
+{
+    sparc_iommu_memory_rw(opaque, addr, buf, len, 1);
+}
+
+/* sparc32_dma.c */
+static void espdma_memory_read(void *opaque, uint8_t *buf, int len);
+static void espdma_memory_write(void *opaque, uint8_t *buf, int len);
+
+#include "tcx.c"
+#include "iommu.c"
+#include "m48t59.c"
+#include "slavio_intctl.c"
+#include "slavio_timer.c"
+#include "slavio_serial.c"
+#include "slavio_misc.c"
+#include "fdc.c"
+#include "esp.c"
+#include "sparc32_dma.c"
+#include "cs4231.c"
+#include "ptimer.c"
+
 //#define DEBUG_IRQ
 
 /*
Index: qemu/hw/tcx.c
===================================================================
--- qemu.orig/hw/tcx.c	2007-11-04 08:17:00.000000000 +0000
+++ qemu/hw/tcx.c	2007-11-04 08:20:41.000000000 +0000
@@ -488,9 +488,10 @@
     tcx_dummy_writel,
 };
 
-void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base,
-              unsigned long vram_offset, int vram_size, int width, int height,
-              int depth)
+static void tcx_init(DisplayState *ds, target_phys_addr_t addr,
+                     uint8_t *vram_base,
+                     unsigned long vram_offset, int vram_size,
+                     int width, int height, int depth)
 {
     TCXState *s;
     int io_memory, dummy_memory;
Index: qemu/vl.h
===================================================================
--- qemu.orig/vl.h	2007-11-04 08:17:00.000000000 +0000
+++ qemu/vl.h	2007-11-04 08:20:41.000000000 +0000
@@ -1245,37 +1245,6 @@
 /* sun4m.c */
 extern QEMUMachine ss5_machine, ss10_machine;
 
-/* iommu.c */
-void *iommu_init(target_phys_addr_t addr);
-void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
-                                 uint8_t *buf, int len, int is_write);
-static inline void sparc_iommu_memory_read(void *opaque,
-                                           target_phys_addr_t addr,
-                                           uint8_t *buf, int len)
-{
-    sparc_iommu_memory_rw(opaque, addr, buf, len, 0);
-}
-
-static inline void sparc_iommu_memory_write(void *opaque,
-                                            target_phys_addr_t addr,
-                                            uint8_t *buf, int len)
-{
-    sparc_iommu_memory_rw(opaque, addr, buf, len, 1);
-}
-
-/* tcx.c */
-void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base,
-              unsigned long vram_offset, int vram_size, int width, int height,
-              int depth);
-
-/* slavio_intctl.c */
-void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
-                         const uint32_t *intbit_to_level,
-                         qemu_irq **irq, qemu_irq **cpu_irq,
-                         qemu_irq **parent_irq, unsigned int cputimer);
-void slavio_pic_info(void *opaque);
-void slavio_irq_info(void *opaque);
-
 /* loader.c */
 int get_image_size(const char *filename);
 int load_image(const char *filename, uint8_t *addr);
@@ -1284,38 +1253,11 @@
 int load_aout(const char *filename, uint8_t *addr);
 int load_uboot(const char *filename, target_ulong *ep, int *is_linux);
 
-/* slavio_timer.c */
-void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq,
-                           qemu_irq *cpu_irqs);
-
-/* slavio_serial.c */
-SerialState *slavio_serial_init(target_phys_addr_t base, qemu_irq irq,
-                                CharDriverState *chr1, CharDriverState *chr2);
-void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq);
-
-/* slavio_misc.c */
-void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
-                       qemu_irq irq);
-void slavio_set_power_fail(void *opaque, int power_failing);
-
-/* esp.c */
-void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id);
-void *esp_init(BlockDriverState **bd, target_phys_addr_t espaddr,
-               void *dma_opaque, qemu_irq irq, qemu_irq *reset);
-
 /* sparc32_dma.c */
-void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
-                       void *iommu, qemu_irq **dev_irq, qemu_irq **reset);
 void ledma_memory_read(void *opaque, target_phys_addr_t addr,
                        uint8_t *buf, int len, int do_bswap);
 void ledma_memory_write(void *opaque, target_phys_addr_t addr,
                         uint8_t *buf, int len, int do_bswap);
-void espdma_memory_read(void *opaque, uint8_t *buf, int len);
-void espdma_memory_write(void *opaque, uint8_t *buf, int len);
-
-/* cs4231.c */
-void cs_init(target_phys_addr_t base, int irq, void *intctl);
-
 /* sun4u.c */
 extern QEMUMachine sun4u_machine;