From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Ip4Ir-0000ld-W2 for qemu-devel@nongnu.org; Mon, 05 Nov 2007 10:55:54 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Ip4Iq-0000kr-CG for qemu-devel@nongnu.org; Mon, 05 Nov 2007 10:55:53 -0500 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Ip4Iq-0000ko-5E for qemu-devel@nongnu.org; Mon, 05 Nov 2007 10:55:52 -0500 Received: from nf-out-0910.google.com ([64.233.182.184]) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1Ip4Ip-0001r3-Ne for qemu-devel@nongnu.org; Mon, 05 Nov 2007 10:55:51 -0500 Received: by nf-out-0910.google.com with SMTP id 30so1326319nfu for ; Mon, 05 Nov 2007 07:55:49 -0800 (PST) Message-ID: Date: Mon, 5 Nov 2007 17:55:47 +0200 From: "Blue Swirl" Subject: Re: [Qemu-devel] sparc hflags support? In-Reply-To: <472E5919.80307@earthlink.net> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Content-Disposition: inline References: <472E5919.80307@earthlink.net> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org On 11/5/07, Robert Reif wrote: > I'm looking at adding more complete support for different sparc32 > CPUs, MMUs, cache controllers and systems. Great! The only problems I see are that OpenBIOS support needs to be added for the new CPUs and supporting all CPUs with one image may become a bit complex. > Each CPU/MMU/cache controller combination is slightly different and > requires its own unique state. For example the two CPUs currently > supported save the boot mode in different bits in the MMU control > register: 0x2000 for the SuperSparc and 0x4000 for the TurboSparc. > Others bits will need to be saved in the MMU and cache controllers > as better hardware emulation is added. I think other targets have better design for supporting different CPU types, for example MIPS and PPC. > It looks like other architectures handle this by computing hflags > in the target directories but sparc determines the flags value to save > in common code. > > Are there plans to add hflags support to sparc? I'm willing work > on it but I don't have the experience yet to tackle a job like this > without help. It could bring some performance benefit. Just try to move the tb flags computation to op_helper.c. Every time hflags elements change, recompute the flags. I'd be happy to try to help you.