From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43)
	id 1IpVOA-0000eh-TM
	for qemu-devel@nongnu.org; Tue, 06 Nov 2007 15:51:11 -0500
Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43)
	id 1IpVO9-0000du-7M
	for qemu-devel@nongnu.org; Tue, 06 Nov 2007 15:51:09 -0500
Received: from [199.232.76.173] (helo=monty-python.gnu.org)
	by lists.gnu.org with esmtp (Exim 4.43) id 1IpVO8-0000dm-UH
	for qemu-devel@nongnu.org; Tue, 06 Nov 2007 15:51:08 -0500
Received: from ik-out-1112.google.com ([66.249.90.183])
	by monty-python.gnu.org with esmtp (Exim 4.60)
	(envelope-from <blauwirbel@gmail.com>) id 1IpVO8-0004v5-Gd
	for qemu-devel@nongnu.org; Tue, 06 Nov 2007 15:51:08 -0500
Received: by ik-out-1112.google.com with SMTP id c29so1295197ika
	for <qemu-devel@nongnu.org>; Tue, 06 Nov 2007 12:51:07 -0800 (PST)
Message-ID: <f43fc5580711061251l763d73bbl8380279557fd781f@mail.gmail.com>
Date: Tue, 6 Nov 2007 22:51:06 +0200
From: "Blue Swirl" <blauwirbel@gmail.com>
Subject: Re: [Qemu-devel] [PATCH] sparc32 boot mode flag fix
In-Reply-To: <200711062039.12196.paul@codesourcery.com>
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 7bit
Content-Disposition: inline
References: <472FD561.7020006@earthlink.net>
	<f43fc5580711061131s29b0d0bbt5f5a5967cc37498d@mail.gmail.com>
	<200711062039.12196.paul@codesourcery.com>
Reply-To: qemu-devel@nongnu.org
List-Id: qemu-devel.nongnu.org
List-Unsubscribe: <http://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.gnu.org/pipermail/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <http://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: Paul Brook <paul@codesourcery.com>
Cc: qemu-devel@nongnu.org

On 11/6/07, Paul Brook <paul@codesourcery.com> wrote:
> > > This patch also removes the MMU flags from being saved in the
> > > translation block code as a result of an off line discussion with Paul
> > > Brook.
> >
> > I'd like to hear the reasoning behind that. The TBs generated while in
> > boot mode and MMU disabled may contain translations generated from
> > virtual to physical mappings that do not exist when the mode is
> > changed. Boot mode and MMU disable are not used after boot and these
> > bits don't affect translation, so those bits may be less important and
> > not worth the few bits in TB flags.
>
> It think you're confusing the TB cache with the TLB. Each TB is already
> indexed by both physical and virtual address (explicitly in tb_find_slow, and
> implicitly in tb_find_fast because a tlb flush clears env->tb_jmp_cache).
>
> IIUC enabling/disabling boot mode is no different to and other VM change. If
> the virtual->physical mapping happens to be the same then it's perfectly ok
> to reuse the TB.

Not in this case: in boot mode, physical and virtual address 0
generates TBs from PROM code. When control transfers to OS in normal
MMU mode, virtual and physical address 0 generates TBs from code in
RAM.

> The TLB is already flushed whenever the MMU mode is changes. There is no need
> to invalidate the TB.

The TB is valid, but only when the boot mode bit is the same as
recorded in the TB flags.