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Date: Thu, 15 Nov 2007 20:10:39 +0200
From: "Blue Swirl" <blauwirbel@gmail.com>
Subject: Re: [Qemu-devel] [RFC][PATCH] fix sparc32 mxcc 64 bit read word order
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To: qemu-devel@nongnu.org

On 11/15/07, Robert Reif <reif@earthlink.net> wrote:
> This patch fixes the word order for 64 bit reads of the mxcc registers.
>
> It returns the high 32 bits in ret and the lower 32 bits in T0 just
> like other places in the same function.
>
> T0 is defined as: register uint32_t T0 asm(AREG1);
>
> T0 on my machine has a sizeof = 4.  Because of this, I don't think
> it is necessary to mask off the high bits with 0xffffffff like other
> places in the same function.  You should probably use 0xffffffffULL to
> mask off the upper 32 bits.
>
> I would remove the & 0xffffffff but I hesitate because T0 is defined
> "register" uint32_t and I'm not sure what that would really be on 64
> bit machines,

On my x86_64 sizeof(T0) is also 4. Only if I replace uint32_t with
long or uint64_t the size becomes 8, with short the size is 2.

> Is this patch correct or should I remove the & 0xffffffff here and in
> the other
> places in the same function or change them to 0xffffffffULL?

I think it's better to remove them, preferably with a different patch
without other changes.