From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1ItJsv-0000lj-FW for qemu-devel@nongnu.org; Sat, 17 Nov 2007 04:22:41 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1ItJsq-0000hk-C6 for qemu-devel@nongnu.org; Sat, 17 Nov 2007 04:22:40 -0500 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1ItJsq-0000hg-7S for qemu-devel@nongnu.org; Sat, 17 Nov 2007 04:22:36 -0500 Received: from nf-out-0910.google.com ([64.233.182.191]) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1ItJsp-0002pK-Rz for qemu-devel@nongnu.org; Sat, 17 Nov 2007 04:22:36 -0500 Received: by nf-out-0910.google.com with SMTP id 30so1091389nfu for ; Sat, 17 Nov 2007 01:22:34 -0800 (PST) Message-ID: Date: Sat, 17 Nov 2007 11:22:34 +0200 From: "Blue Swirl" Subject: Re: [Qemu-devel] [PATCH] sparc32 fix MXCC error bit clearing In-Reply-To: <473CD6AE.8090309@earthlink.net> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Content-Disposition: inline References: <473CD6AE.8090309@earthlink.net> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org On 11/16/07, Robert Reif wrote: > Fix MXCC error register bit clearing. Thanks, applied.