From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1ItLdQ-0000D0-Tc for qemu-devel@nongnu.org; Sat, 17 Nov 2007 06:14:48 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1ItLdP-0000Ck-75 for qemu-devel@nongnu.org; Sat, 17 Nov 2007 06:14:47 -0500 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1ItLdP-0000Ch-2t for qemu-devel@nongnu.org; Sat, 17 Nov 2007 06:14:47 -0500 Received: from nf-out-0910.google.com ([64.233.182.187]) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1ItLdO-0001Eg-SB for qemu-devel@nongnu.org; Sat, 17 Nov 2007 06:14:47 -0500 Received: by nf-out-0910.google.com with SMTP id 30so1106488nfu for ; Sat, 17 Nov 2007 03:14:45 -0800 (PST) Message-ID: Date: Sat, 17 Nov 2007 13:14:44 +0200 From: "Blue Swirl" Subject: Re: [Qemu-devel] qemu softmmu_template.h In-Reply-To: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Content-Disposition: inline References: <1195293653.5335.27.camel@rapid> <1195295212.5335.36.camel@rapid> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org On 11/17/07, andrzej zaborowski wrote: > On 17/11/2007, J. Mayer wrote: > > > > On Sat, 2007-11-17 at 11:14 +0100, andrzej zaborowski wrote: > > > On 17/11/2007, J. Mayer wrote: > > > > > > > > On Sat, 2007-11-17 at 09:53 +0000, Andrzej Zaborowski wrote: > > > > > CVSROOT: /sources/qemu > > > > > Module name: qemu > > > > > Changes by: Andrzej Zaborowski 07/11/17 09:53:42 > > > > > > > > > > Modified files: > > > > > . : softmmu_template.h > > > > > > > > > > Log message: > > > > > Check permissions for the last byte first in unaligned slow_st accesses (patch from TeLeMan). > > > > > > > > > > CVSWeb URLs: > > > > > http://cvs.savannah.gnu.org/viewcvs/qemu/softmmu_template.h?cvsroot=qemu&r1=1.19&r2=1.20 > > > > > > > > > > > > > Has it been checked that it's legal for all architectures and cannot > > > > have any nasty side effect to do accesses in the reverse order ? Real > > > > hardware do not ever seem to do this... > > > > > > For real hardware the store is a single operation. > > > > For PowerPC, at least, only aligned stores are defined as atomic. It's > > absolutely legal for an implementation to split all non-atomic accesses > > into smaller aligned accesses. And I guess it is the same for all > > architecture that can do unaligned accesses. > > > > > Logically it shouldn't have any side effects, but if it does then it > > > would rather mean that other code for that architecture is (also) > > > broken, I believe. > > > > > > I've only tested ARM, mips, x86 and x86_64 before committing, so > > > please test. I figured that the patch won't get any comments on the > > > mailing list if it isn't merged. > > > > I don't think it's so easy to test because it may be very hard to > > trigger the cases that would have side effects, which are target > > dependent. I then am very curious to know how you did check that there > > is no problem with this patch.... > > Well, for ARM, x86 and x86_64 I only checked that unaligned accesses > still work, i.e. that I haven't made an obvious typo. I haven't tested > cross-page accesses with the access to the second page being invalid, > I also don't know how the specifications for other architectures > define the effect of such accesses, so maybe I shouldn't have > committed this, but I assumed a common sense in the design of cpu > archs, meaning that in the example given by TeLeMan the addition is > not performed two times on some bytes. Sparc is unaffected, unaligned accesses are forbidden.