From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1IzF32-0006Sy-10 for qemu-devel@nongnu.org; Mon, 03 Dec 2007 12:25:36 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1IzF30-0006Rw-8p for qemu-devel@nongnu.org; Mon, 03 Dec 2007 12:25:35 -0500 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1IzF30-0006Rt-2D for qemu-devel@nongnu.org; Mon, 03 Dec 2007 12:25:34 -0500 Received: from ug-out-1314.google.com ([66.249.92.172]) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1IzF2z-0004M0-1t for qemu-devel@nongnu.org; Mon, 03 Dec 2007 12:25:33 -0500 Received: by ug-out-1314.google.com with SMTP id m2so2374211uge for ; Mon, 03 Dec 2007 09:25:31 -0800 (PST) Message-ID: Date: Mon, 3 Dec 2007 19:25:31 +0200 From: "Blue Swirl" Subject: Re: [Qemu-devel] [PATCH] sparc32 machine specific maximums In-Reply-To: <47533BD3.4000606@earthlink.net> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Content-Disposition: inline References: <47533BD3.4000606@earthlink.net> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org On 12/3/07, Robert Reif wrote: > This patch sets the maximum number of CPUs and memory to what is > supported by the actual hardware. While it's not historically accurate to emulate a Sparcstation 5 with 16 CPUs and 2 gigabytes of memory, it doesn't break anything to have this capability. We don't throttle the power of the CPU, speed of the network, serial or disk devices either, so they may be unrealistically fast. The timers are not accurate at all compared to CPU execution speed. Currently the memory on SS-5 machine is limited by the location of IOMMU and that the memory lies in one linear bank starting from zero. With more advanced banking and >4G patches, the entire physical address space could be filled with RAM.