From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1JU5tT-0000MW-Vp for qemu-devel@nongnu.org; Tue, 26 Feb 2008 14:55:16 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1JU5tQ-0000HF-UN for qemu-devel@nongnu.org; Tue, 26 Feb 2008 14:55:15 -0500 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1JU5tQ-0000Gs-Kl for qemu-devel@nongnu.org; Tue, 26 Feb 2008 14:55:12 -0500 Received: from ug-out-1314.google.com ([66.249.92.169]) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1JU5tP-0007tj-Kl for qemu-devel@nongnu.org; Tue, 26 Feb 2008 14:55:11 -0500 Received: by ug-out-1314.google.com with SMTP id m2so1496918uge.4 for ; Tue, 26 Feb 2008 11:55:09 -0800 (PST) Message-ID: Date: Tue, 26 Feb 2008 21:55:08 +0200 From: "Blue Swirl" MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="----=_Part_12879_12014613.1204055708938" Subject: [Qemu-devel] TCG on i386 can't generate qemu_st64 for 32-bit target Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Fabrice Bellard Cc: qemu-devel ------=_Part_12879_12014613.1204055708938 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Content-Disposition: inline Hi, There is a problem with the Sparc32 target on i386 host. Store double word op (std) cannot be generated and TCG just aborts. It looks like the registers are so few on i386 that TCG can't find registers for the qemu_st64 call. The problem does not appear on x86_64 host, or for Sparc64 target (stx/ldx) on i386, or with 64-bit load (ldd) on Sparc32 target. The attached patch would work around the problem, but I agree that it's ugly and it would bring back one instance of T2 use. I also tried preallocating a 64-bit register but that didn't help. I suppose instead the following piece (tcg/i386/tcg-target.c:737) could be modified to lower the pressure for registers but I'm not that familiar with x86 assembly. #if TARGET_LONG_BITS == 32 if (opc == 3) { tcg_out_mov(s, TCG_REG_EDX, data_reg); tcg_out_mov(s, TCG_REG_ECX, data_reg2); tcg_out8(s, 0x6a); /* push Ib */ tcg_out8(s, mem_index); tcg_out8(s, 0xe8); tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] - (tcg_target_long)s->code_ptr - 4); tcg_out_addi(s, TCG_REG_ESP, 4); } else { ------=_Part_12879_12014613.1204055708938 Content-Type: text/x-diff; name=std_fix_i386.diff Content-Transfer-Encoding: base64 X-Attachment-Id: f_fd4vhrdp Content-Disposition: attachment; filename=std_fix_i386.diff SW5kZXg6IHFlbXUvdGFyZ2V0LXNwYXJjL3RyYW5zbGF0ZS5jCj09PT09PT09PT09PT09PT09PT09 PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT0KLS0tIHFlbXUu b3JpZy90YXJnZXQtc3BhcmMvdHJhbnNsYXRlLmMJMjAwOC0wMi0yNiAxOTo0ODozOC4wMDAwMDAw MDAgKzAwMDAKKysrIHFlbXUvdGFyZ2V0LXNwYXJjL3RyYW5zbGF0ZS5jCTIwMDgtMDItMjYgMTk6 NDg6MzguMDAwMDAwMDAwICswMDAwCkBAIC0xOTIsNiArMTkyLDkgQEAKICNlbmRpZgogCiAjaWZu ZGVmIENPTkZJR19VU0VSX09OTFkKKyNpZmRlZiBfX2kzODZfXworT1BfTERfVEFCTEUoc3RkKTsK KyNlbmRpZiAvKiBfX2kzODZfXyAqLwogT1BfTERfVEFCTEUoc3RmKTsKIE9QX0xEX1RBQkxFKHN0 ZGYpOwogT1BfTERfVEFCTEUobGRmKTsKQEAgLTIzMSw2ICsyMzQsMTMgQEAKICAgICBnZW5fbW92 bF9yZWdfVE4ocmVnLCBjcHVfVFsxXSk7CiB9CiAKKyNpZmRlZiBfX2kzODZfXworc3RhdGljIGlu bGluZSB2b2lkIGdlbl9tb3ZsX3JlZ19UMihpbnQgcmVnKQoreworICAgIGdlbl9tb3ZsX3JlZ19U TihyZWcsIGNwdV9UWzJdKTsKK30KKworI2VuZGlmIC8qIF9faTM4Nl9fICovCiBzdGF0aWMgaW5s aW5lIHZvaWQgZ2VuX21vdmxfVE5fcmVnKGludCByZWcsIFRDR3YgdG4pCiB7CiAgICAgaWYgKHJl ZyA9PSAwKQpAQCAtMzI3NSw2ICszMjg1LDcgQEAKICAgICAgICAgICAgICAgICBjYXNlIDB4Nzog Lyogc3RvcmUgZG91YmxlIHdvcmQgKi8KICAgICAgICAgICAgICAgICAgICAgaWYgKHJkICYgMSkK ICAgICAgICAgICAgICAgICAgICAgICAgIGdvdG8gaWxsZWdhbF9pbnNuOworI2lmbmRlZiBfX2kz ODZfXwogICAgICAgICAgICAgICAgICAgICBlbHNlIHsKICAgICAgICAgICAgICAgICAgICAgICAg IFRDR3Ygcl9kd29yZCwgcl9sb3c7CiAKQEAgLTMyODYsNiArMzI5NywxMiBAQAogICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIHJfbG93KTsKICAgICAgICAgICAgICAg ICAgICAgICAgIHRjZ19nZW5fcWVtdV9zdDY0KHJfZHdvcmQsIGNwdV9UWzBdLCBkYy0+bWVtX2lk eCk7CiAgICAgICAgICAgICAgICAgICAgIH0KKyNlbHNlIC8qIF9faTM4Nl9fICovCisgICAgICAg ICAgICAgICAgICAgIGdlbl9vcF9jaGVja19hbGlnbl9UMF83KCk7CisgICAgICAgICAgICAgICAg ICAgIGZsdXNoX1QyKGRjKTsKKyAgICAgICAgICAgICAgICAgICAgZ2VuX21vdmxfcmVnX1QyKHJk ICsgMSk7CisgICAgICAgICAgICAgICAgICAgIGdlbl9vcF9sZHN0KHN0ZCk7CisjZW5kaWYgLyog X19pMzg2X18gKi8KICAgICAgICAgICAgICAgICAgICAgYnJlYWs7CiAjaWYgIWRlZmluZWQoQ09O RklHX1VTRVJfT05MWSkgfHwgZGVmaW5lZChUQVJHRVRfU1BBUkM2NCkKICAgICAgICAgICAgICAg ICBjYXNlIDB4MTQ6IC8qIHN0b3JlIHdvcmQgYWx0ZXJuYXRlICovCkluZGV4OiBxZW11L3Rhcmdl dC1zcGFyYy9vcF9tZW0uaAo9PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09 PT09PT09PT09PT09PT09PT09PT09PT09PT09Ci0tLSBxZW11Lm9yaWcvdGFyZ2V0LXNwYXJjL29w X21lbS5oCTIwMDgtMDItMjYgMTk6NDg6MzguMDAwMDAwMDAwICswMDAwCisrKyBxZW11L3Rhcmdl dC1zcGFyYy9vcF9tZW0uaAkyMDA4LTAyLTI2IDE5OjQ4OjM4LjAwMDAwMDAwMCArMDAwMApAQCAt NCw2ICs0LDE2IEBACiAjZGVmaW5lIEFERFIoeCkgKHgpCiAjZW5kaWYKIAorI2lmZGVmIF9faTM4 Nl9fCisvKioqICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgSW50ZWdlciBzdG9yZSAgICAg ICAgICAgICAgICAgICAgICAgICAgICAqKiovCit2b2lkIE9QUFJPVE8gZ2x1ZShvcF9zdGQsIE1F TVNVRkZJWCkodm9pZCkKK3sKKyAgICB1aW50NjRfdCB0bXAgPSAoKHVpbnQ2NF90KVQxIDw8IDMy KSB8ICh1aW50NjRfdCkoVDIgJiAweGZmZmZmZmZmKTsKKworICAgIGdsdWUoc3RxLCBNRU1TVUZG SVgpKEFERFIoVDApLCB0bXApOworfQorCisjZW5kaWYgLyogX19pMzg2X18gKi8KIC8qKiogICAg ICAgICAgICAgICAgICAgICAgICAgRmxvYXRpbmctcG9pbnQgc3RvcmUgICAgICAgICAgICAgICAg ICAgICAgICAgICoqKi8KIHZvaWQgT1BQUk9UTyBnbHVlKG9wX3N0ZiwgTUVNU1VGRklYKSAodm9p ZCkKIHsK ------=_Part_12879_12014613.1204055708938--