[Qemu-devel] [PATCH] sparc64 correct 32bit carry flag for add instruction

[Qemu-devel] [PATCH] sparc64 correct 32bit carry flag for add instruction

[Igor Kovalenko]

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Hi!

The attached sparc64-add-carry-icc.patch should fix a problem with
setting 32bit carry flag after add instruction.
This at least fixes a problem with silo vprinf printing only least
significant digit of integers (now it can output address where it
loads kernel instead of 0x0)

Please apply.

-- 
Kind regards,
Igor V. Kovalenko

[-- Attachment #2: sparc64-add-carry-icc.patch --]
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Index: target-sparc/translate.c
===================================================================
--- target-sparc/translate.c	(revision 5012)
+++ target-sparc/translate.c	(working copy)
@@ -349,16 +349,19 @@
 */
 static inline void gen_cc_C_add_icc(TCGv dst, TCGv src1)
 {
-    TCGv r_temp;
+    TCGv r_temp1, r_temp2;
     int l1;
 
     l1 = gen_new_label();
-    r_temp = tcg_temp_new(TCG_TYPE_TL);
-    tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
-    tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1);
+    r_temp1 = tcg_temp_new(TCG_TYPE_TL);
+    r_temp2 = tcg_temp_new(TCG_TYPE_TL);
+    tcg_gen_andi_tl(r_temp1, dst, 0xffffffffULL);
+    tcg_gen_andi_tl(r_temp2, src1, 0xffffffffULL);
+    tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1);
     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
     gen_set_label(l1);
-    tcg_temp_free(r_temp);
+    tcg_temp_free(r_temp1);
+    tcg_temp_free(r_temp2);
 }
 
 #ifdef TARGET_SPARC64

Re: [Qemu-devel] [PATCH] sparc64 correct 32bit carry flag for add instruction

[Blue Swirl]

On 8/17/08, Igor Kovalenko <igor.v.kovalenko@gmail.com> wrote:
> Hi!
>
>  The attached sparc64-add-carry-icc.patch should fix a problem with
>  setting 32bit carry flag after add instruction.
>  This at least fixes a problem with silo vprinf printing only least
>  significant digit of integers (now it can output address where it
>  loads kernel instead of 0x0)
>
>  Please apply.

Thanks, applied.