From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1KZAdP-0007sJ-75 for qemu-devel@nongnu.org; Fri, 29 Aug 2008 16:31:55 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1KZAdN-0007rs-Ia for qemu-devel@nongnu.org; Fri, 29 Aug 2008 16:31:54 -0400 Received: from [199.232.76.173] (port=35174 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1KZAdN-0007rp-Ep for qemu-devel@nongnu.org; Fri, 29 Aug 2008 16:31:53 -0400 Received: from wf-out-1314.google.com ([209.85.200.173]:43250) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1KZAdM-000313-Uu for qemu-devel@nongnu.org; Fri, 29 Aug 2008 16:31:53 -0400 Received: by wf-out-1314.google.com with SMTP id 27so925339wfd.4 for ; Fri, 29 Aug 2008 13:31:51 -0700 (PDT) Message-ID: Date: Fri, 29 Aug 2008 23:31:51 +0300 From: "Blue Swirl" Subject: Re: [Qemu-devel] sparc 64-bit fsr problem In-Reply-To: <20080829160107.N71741@stanley.csl.cornell.edu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Content-Disposition: inline References: <20080828172114.V64752@stanley.csl.cornell.edu> <20080829160107.N71741@stanley.csl.cornell.edu> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org On 8/29/08, Vince Weaver wrote: > > > > I've attempted to fix this myself but I am having trouble trying to get > the gen_mov_reg_FCC0() and gen_mov_reg_FCC1() functions in > target-sparc/translate.c to use 64-bit shifts. I think the fsr bit definitions in cpu.h need to be changed from 1< I've managed to get things working, at least enough to run equake from the > spec2k benchmarks. The patch is below. Thanks for the debugging by the way! > > > Vince > > --- op_helper.c.orig 2008-08-28 17:25:22.000000000 -0400 > +++ op_helper.c 2008-08-28 17:27:42.000000000 -0400 > @@ -746,10 +746,10 @@ > { \ > target_ulong new_fsr; \ > \ > - env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \ > + env->fsr &= ~((target_ulong) (FSR_FCC1 | FSR_FCC0) << FS); \ > switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \ > case float_relation_unordered: \ > - new_fsr = (FSR_FCC1 | FSR_FCC0) << FS; \ > + new_fsr = (target_ulong)(FSR_FCC1 | FSR_FCC0) << FS; \ > if ((env->fsr & FSR_NVM) || TRAP) { \ > env->fsr |= new_fsr; \ > env->fsr |= FSR_NVC; \ > @@ -760,10 +760,10 @@ > } \ > break; \ > case float_relation_less: \ > - new_fsr = FSR_FCC0 << FS; \ > + new_fsr = (target_ulong)FSR_FCC0 << FS; \ > break; \ > case float_relation_greater: \ > - new_fsr = FSR_FCC1 << FS; \ > + new_fsr = (target_ulong)FSR_FCC1 << FS; \ > break; \ > default: \ > new_fsr = 0; \ > --- translate.c.orig 2008-08-29 15:59:15.000000000 -0400 > +++ translate.c 2008-08-29 15:59:57.000000000 -0400 > @@ -999,7 +999,7 @@ > static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src, > unsigned int fcc_offset) > { > - tcg_gen_extu_i32_tl(reg, src); > + tcg_gen_mov_tl(reg, src); > tcg_gen_shri_tl(reg, reg, FSR_FCC0_SHIFT + fcc_offset); Drop the mov and: tcg_gen_shri_tl(reg, src FSR_FCC0_SHIFT + fcc_offset); > tcg_gen_andi_tl(reg, reg, 0x1); > } > @@ -1007,7 +1007,7 @@ > static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src, > unsigned int fcc_offset) > { > - tcg_gen_extu_i32_tl(reg, src); > + tcg_gen_mov_tl(reg, src); > tcg_gen_shri_tl(reg, reg, FSR_FCC1_SHIFT + fcc_offset); Same here. > tcg_gen_andi_tl(reg, reg, 0x1); > }