Index: qemu/hw/fw_cfg.c
===================================================================
--- qemu.orig/hw/fw_cfg.c	2008-08-30 15:15:48.000000000 +0000
+++ qemu/hw/fw_cfg.c	2008-08-30 19:16:22.000000000 +0000
@@ -160,6 +160,10 @@
     return 1;
 }
 
+extern int nographic;
+static uint8_t cfg_nographic;
+static uint16_t cfg_nb_cpus;
+
 void *fw_cfg_init(uint32_t port, target_phys_addr_t addr)
 {
     FWCfgState *s;
@@ -181,6 +185,10 @@
     }
     fw_cfg_add(s, FW_CFG_SIGNATURE, (uint8_t *)"QEMU", 4);
     fw_cfg_add(s, FW_CFG_UUID, qemu_uuid, 16);
+    cfg_nographic = (uint8_t)nographic;
+    fw_cfg_add(s, FW_CFG_NOGRAPHIC, &cfg_nographic, sizeof(cfg_nographic));
+    cfg_nb_cpus = cpu_to_le16((uint16_t)smp_cpus);
+    fw_cfg_add(s, FW_CFG_NB_CPUS, (uint8_t *)&cfg_nb_cpus, sizeof(cfg_nb_cpus));
     register_savevm("fw_cfg", -1, 1, fw_cfg_save, fw_cfg_load, s);
     qemu_register_reset(fw_cfg_reset, s);
     fw_cfg_reset(s);
Index: qemu/hw/fw_cfg.h
===================================================================
--- qemu.orig/hw/fw_cfg.h	2008-08-30 15:15:48.000000000 +0000
+++ qemu/hw/fw_cfg.h	2008-08-30 15:15:54.000000000 +0000
@@ -4,6 +4,10 @@
 #define FW_CFG_SIGNATURE        0x00
 #define FW_CFG_ID               0x01
 #define FW_CFG_UUID             0x02
+#define FW_CFG_RAM_SIZE         0x03
+#define FW_CFG_NOGRAPHIC        0x04
+#define FW_CFG_NB_CPUS          0x05
+#define FW_CFG_MACHINE_ID       0x06
 #define FW_CFG_MAX_ENTRY        0x10
 
 #define FW_CFG_ARCH_LOCAL       0x8000
Index: qemu/hw/sun4u.c
===================================================================
--- qemu.orig/hw/sun4u.c	2008-08-30 15:15:23.000000000 +0000
+++ qemu/hw/sun4u.c	2008-08-30 15:17:46.000000000 +0000
@@ -49,6 +49,7 @@
 
 struct hwdef {
     const char * const default_cpu_model;
+    uint8_t machine_id;
 };
 
 int DMA_get_channel_mode (int nchan)
@@ -255,6 +256,7 @@
 static fdctrl_t *floppy_controller;
 
 static uint32_t bios_cfg_id;
+static uint64_t bios_cfg_ram_size;
 
 static void sun4uv_init(ram_addr_t RAM_size, int vga_ram_size,
                         const char *boot_devices, DisplayState *ds,
@@ -424,16 +426,28 @@
     bios_cfg_id = cpu_to_le32(1);
     fw_cfg_add(fw_cfg, FW_CFG_ID, (uint8_t *)&bios_cfg_id,
                sizeof(bios_cfg_id));
+    bios_cfg_ram_size = cpu_to_le64(ram_size);
+    fw_cfg_add(fw_cfg, FW_CFG_RAM_SIZE, (uint8_t *)&bios_cfg_ram_size,
+               sizeof(bios_cfg_ram_size));
+    fw_cfg_add(fw_cfg, FW_CFG_MACHINE_ID, &hwdef->machine_id,
+               sizeof(hwdef->machine_id));
 }
 
+enum {
+    sun4u_id = 0,
+    sun4v_id = 64,
+};
+
 static const struct hwdef hwdefs[] = {
     /* Sun4u generic PC-like machine */
     {
         .default_cpu_model = "TI UltraSparc II",
+        .machine_id = sun4u_id,
     },
     /* Sun4v generic PC-like machine */
     {
         .default_cpu_model = "Sun UltraSparc T1",
+        .machine_id = sun4v_id,
     },
 };
 
Index: qemu/hw/pc.c
===================================================================
--- qemu.orig/hw/pc.c	2008-08-30 15:15:51.000000000 +0000
+++ qemu/hw/pc.c	2008-08-30 15:15:54.000000000 +0000
@@ -502,6 +502,7 @@
 }
 
 static uint32_t bios_cfg_id;
+static uint64_t bios_cfg_ram_size;
 
 static void bochs_bios_init(void)
 {
@@ -527,6 +528,9 @@
                sizeof(bios_cfg_id));
     fw_cfg_add(fw_cfg, FW_CFG_PC_CPUSPEED, (uint8_t*)&cpu_speed,
                sizeof(cpu_speed));
+    bios_cfg_ram_size = cpu_to_le64(ram_size);
+    fw_cfg_add(fw_cfg, FW_CFG_RAM_SIZE, (uint8_t *)&bios_cfg_ram_size,
+               sizeof(bios_cfg_ram_size));
 }
 
 /* Generate an initial boot sector which sets state and jump to
Index: qemu/hw/sun4m.c
===================================================================
--- qemu.orig/hw/sun4m.c	2008-08-30 15:15:23.000000000 +0000
+++ qemu/hw/sun4m.c	2008-08-30 15:32:09.000000000 +0000
@@ -101,7 +101,8 @@
     // register bit numbers
     int intctl_g_intr, esp_irq, le_irq, clock_irq, clock1_irq;
     int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq, ecc_irq;
-    int machine_id; // For NVRAM
+    uint8_t nvram_machine_id;
+    uint8_t machine_id;
     uint32_t iommu_version;
     uint32_t intbit_to_level[32];
     uint64_t max_mem;
@@ -122,7 +123,8 @@
     // IRQ numbers are not PIL ones, but SBI register bit numbers
     int esp_irq, le_irq, clock_irq, clock1_irq;
     int ser_irq, ms_kb_irq, me_irq;
-    int machine_id; // For NVRAM
+    uint8_t nvram_machine_id;
+    uint8_t machine_id;
     uint32_t iounit_version;
     uint64_t max_mem;
     const char * const default_cpu_model;
@@ -178,7 +180,7 @@
                        const char *boot_devices, ram_addr_t RAM_size,
                        uint32_t kernel_size,
                        int width, int height, int depth,
-                       int machine_id, const char *arch)
+                       int nvram_machine_id, const char *arch)
 {
     unsigned int i;
     uint32_t start, end;
@@ -251,7 +253,8 @@
     end = 0x1fd0;
     OpenBIOS_finish_partition(part_header, end - start);
 
-    Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, machine_id);
+    Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
+                    nvram_machine_id);
 
     for (i = 0; i < sizeof(image); i++)
         m48t59_write(nvram, i, image[i]);
@@ -394,6 +397,7 @@
 }
 
 static uint32_t bios_cfg_id;
+static uint64_t bios_cfg_ram_size;
 
 static void sun4m_hw_init(const struct hwdef *hwdef, ram_addr_t RAM_size,
                           const char *boot_device,
@@ -570,7 +574,8 @@
 
     nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
                boot_device, RAM_size, kernel_size, graphic_width,
-               graphic_height, graphic_depth, hwdef->machine_id, "Sun4m");
+               graphic_height, graphic_depth, hwdef->nvram_machine_id,
+               "Sun4m");
 
     if (hwdef->ecc_base != (target_phys_addr_t)-1)
         ecc_init(hwdef->ecc_base, slavio_irq[hwdef->ecc_irq],
@@ -580,6 +585,11 @@
     bios_cfg_id = cpu_to_le32(1);
     fw_cfg_add(fw_cfg, FW_CFG_ID, (uint8_t *)&bios_cfg_id,
                sizeof(bios_cfg_id));
+    bios_cfg_ram_size = cpu_to_le64(ram_size);
+    fw_cfg_add(fw_cfg, FW_CFG_RAM_SIZE, (uint8_t *)&bios_cfg_ram_size,
+               sizeof(bios_cfg_ram_size));
+    fw_cfg_add(fw_cfg, FW_CFG_MACHINE_ID, &hwdef->machine_id,
+               sizeof(hwdef->machine_id));
 }
 
 static void sun4c_hw_init(const struct hwdef *hwdef, ram_addr_t RAM_size,
@@ -725,13 +735,34 @@
 
     nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
                boot_device, RAM_size, kernel_size, graphic_width,
-               graphic_height, graphic_depth, hwdef->machine_id, "Sun4c");
+               graphic_height, graphic_depth, hwdef->nvram_machine_id,
+               "Sun4c");
 
     fw_cfg = fw_cfg_init(0, CFG_ADDR);
     bios_cfg_id = cpu_to_le32(1);
     fw_cfg_add(fw_cfg, FW_CFG_ID, (uint8_t *)&bios_cfg_id,
                sizeof(bios_cfg_id));
-}
+    bios_cfg_ram_size = cpu_to_le64(ram_size);
+    fw_cfg_add(fw_cfg, FW_CFG_RAM_SIZE, (uint8_t *)&bios_cfg_ram_size,
+               sizeof(bios_cfg_ram_size));
+    fw_cfg_add(fw_cfg, FW_CFG_MACHINE_ID, &hwdef->machine_id,
+               sizeof(hwdef->machine_id));
+}
+
+enum {
+    ss2_id = 0,
+    ss5_id = 32,
+    ss10_id,
+    ss600mp_id,
+    ss20_id,
+    vger_id,
+    lx_id,
+    ss4_id,
+    scls_id,
+    sbook_id,
+    ss1000_id = 64,
+    ss2000_id,
+};
 
 static const struct hwdef hwdefs[] = {
     /* SS-5 */
@@ -767,7 +798,8 @@
         .fd_irq = 22,
         .me_irq = 30,
         .cs_irq = 5,
-        .machine_id = 0x80,
+        .nvram_machine_id = 0x80,
+        .machine_id = ss5_id,
         .iommu_version = 0x05000000,
         .intbit_to_level = {
             2, 3, 5, 7, 9, 11, 0, 14,   3, 5, 7, 9, 11, 13, 12, 12,
@@ -811,7 +843,8 @@
         .me_irq = 30,
         .cs_irq = -1,
         .ecc_irq = 28,
-        .machine_id = 0x72,
+        .nvram_machine_id = 0x72,
+        .machine_id = ss10_id,
         .iommu_version = 0x03000000,
         .intbit_to_level = {
             2, 3, 5, 7, 9, 11, 0, 14,   3, 5, 7, 9, 11, 13, 12, 12,
@@ -855,7 +888,8 @@
         .me_irq = 30,
         .cs_irq = -1,
         .ecc_irq = 28,
-        .machine_id = 0x71,
+        .nvram_machine_id = 0x71,
+        .machine_id = ss600mp_id,
         .iommu_version = 0x01000000,
         .intbit_to_level = {
             2, 3, 5, 7, 9, 11, 0, 14,   3, 5, 7, 9, 11, 13, 12, 12,
@@ -899,7 +933,8 @@
         .me_irq = 30,
         .cs_irq = -1,
         .ecc_irq = 28,
-        .machine_id = 0x72,
+        .nvram_machine_id = 0x72,
+        .machine_id = ss20_id,
         .iommu_version = 0x13000000,
         .intbit_to_level = {
             2, 3, 5, 7, 9, 11, 0, 14,   3, 5, 7, 9, 11, 13, 12, 12,
@@ -939,7 +974,8 @@
         .fd_irq = 1,
         .me_irq = 1,
         .cs_irq = -1,
-        .machine_id = 0x55,
+        .nvram_machine_id = 0x55,
+        .machine_id = ss2_id,
         .max_mem = 0x10000000,
         .default_cpu_model = "Cypress CY7C601",
     },
@@ -976,7 +1012,8 @@
         .fd_irq = 22,
         .me_irq = 30,
         .cs_irq = -1,
-        .machine_id = 0x80,
+        .nvram_machine_id = 0x80,
+        .machine_id = vger_id,
         .iommu_version = 0x05000000,
         .intbit_to_level = {
             2, 3, 5, 7, 9, 11, 0, 14,   3, 5, 7, 9, 11, 13, 12, 12,
@@ -1018,7 +1055,8 @@
         .fd_irq = 22,
         .me_irq = 30,
         .cs_irq = -1,
-        .machine_id = 0x80,
+        .nvram_machine_id = 0x80,
+        .machine_id = lx_id,
         .iommu_version = 0x04000000,
         .intbit_to_level = {
             2, 3, 5, 7, 9, 11, 0, 14,   3, 5, 7, 9, 11, 13, 12, 12,
@@ -1060,7 +1098,8 @@
         .fd_irq = 22,
         .me_irq = 30,
         .cs_irq = 5,
-        .machine_id = 0x80,
+        .nvram_machine_id = 0x80,
+        .machine_id = ss4_id,
         .iommu_version = 0x05000000,
         .intbit_to_level = {
             2, 3, 5, 7, 9, 11, 0, 14,   3, 5, 7, 9, 11, 13, 12, 12,
@@ -1102,7 +1141,8 @@
         .fd_irq = 22,
         .me_irq = 30,
         .cs_irq = -1,
-        .machine_id = 0x80,
+        .nvram_machine_id = 0x80,
+        .machine_id = scls_id,
         .iommu_version = 0x05000000,
         .intbit_to_level = {
             2, 3, 5, 7, 9, 11, 0, 14,   3, 5, 7, 9, 11, 13, 12, 12,
@@ -1144,7 +1184,8 @@
         .fd_irq = 22,
         .me_irq = 30,
         .cs_irq = -1,
-        .machine_id = 0x80,
+        .nvram_machine_id = 0x80,
+        .machine_id = sbook_id,
         .iommu_version = 0x05000000,
         .intbit_to_level = {
             2, 3, 5, 7, 9, 11, 0, 14,   3, 5, 7, 9, 11, 13, 12, 12,
@@ -1365,7 +1406,8 @@
         .clock1_irq = 10,
         .ms_kb_irq = 12,
         .ser_irq = 12,
-        .machine_id = 0x80,
+        .nvram_machine_id = 0x80,
+        .machine_id = ss1000_id,
         .iounit_version = 0x03000000,
         .max_mem = 0xf00000000ULL,
         .default_cpu_model = "TI SuperSparc II",
@@ -1398,7 +1440,8 @@
         .clock1_irq = 10,
         .ms_kb_irq = 12,
         .ser_irq = 12,
-        .machine_id = 0x80,
+        .nvram_machine_id = 0x80,
+        .machine_id = ss2000_id,
         .iounit_version = 0x03000000,
         .max_mem = 0xf00000000ULL,
         .default_cpu_model = "TI SuperSparc II",
@@ -1544,12 +1587,17 @@
 
     nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
                boot_device, RAM_size, kernel_size, graphic_width,
-               graphic_height, graphic_depth, hwdef->machine_id, "Sun4d");
+               graphic_height, graphic_depth, hwdef->nvram_machine_id, "Sun4d");
 
     fw_cfg = fw_cfg_init(0, CFG_ADDR);
     bios_cfg_id = cpu_to_le32(1);
     fw_cfg_add(fw_cfg, FW_CFG_ID, (uint8_t *)&bios_cfg_id,
                sizeof(bios_cfg_id));
+    bios_cfg_ram_size = cpu_to_le64(ram_size);
+    fw_cfg_add(fw_cfg, FW_CFG_RAM_SIZE, (uint8_t *)&bios_cfg_ram_size,
+               sizeof(bios_cfg_ram_size));
+    fw_cfg_add(fw_cfg, FW_CFG_MACHINE_ID, &hwdef->machine_id,
+               sizeof(hwdef->machine_id));
 }
 
 /* SPARCserver 1000 hardware initialisation */
