From: "Blue Swirl" <blauwirbel@gmail.com>
To: qemu-devel@nongnu.org, Fabrice Bellard <fabrice@bellard.org>
Subject: Re: [Qemu-devel] sparc smul problem
Date: Mon, 1 Sep 2008 22:05:45 +0300 [thread overview]
Message-ID: <f43fc5580809011205l3c3ba867v32006ef0fe1a9cdf@mail.gmail.com> (raw)
In-Reply-To: <20080901121035.R83237@stanley.csl.cornell.edu>
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On 9/1/08, Vince Weaver <vince@csl.cornell.edu> wrote:
> Hello!
>
> I've been stuck on this all weekend, as I can't find where the actual
> problem is. I might be completely missing it, but I've tried a lot of things
> and can't make it work.
>
> On SPARC, the "smul" instruction multiplies two numbers, puts the result in
> the result register but also puts the top 32-bits of the 64-bit result into
> the "Y" register.
>
> As the attached code shows, the value of "Y" is wrong. Somehow after the
> multiply, the top 32 bits of the product rae all zeros. I've played around
> with the code generated by translate.c, and it looks like the shift and
> other instructions all work properly, but the 64-bit multiply the result is
> somehow being truncated. But I've looked at the generated code (on x86_64)
> and it looks like it is doing the right thing.
>
> So anyway, I'll have to take a look at this again later, but in case anyone
> else wants to look at it in case I am missing anything obvious.
It looks like TCG on i386 host generates incorrect code for mulu2_i32,
I think the op should be imul (unsigned) instead of mul. This patch
fixes the problem.
[-- Attachment #2: fix_tcg_i386_mulu2.diff --]
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next prev parent reply other threads:[~2008-09-01 19:05 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-09-01 16:14 [Qemu-devel] sparc smul problem Vince Weaver
2008-09-01 16:49 ` Blue Swirl
2008-09-01 17:20 ` Blue Swirl
2008-09-01 19:05 ` Blue Swirl [this message]
2008-09-01 23:11 ` Aurelien Jarno
2008-09-02 16:58 ` Blue Swirl
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