From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1KaEij-0000jD-3L for qemu-devel@nongnu.org; Mon, 01 Sep 2008 15:05:49 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1KaEih-0000iz-3E for qemu-devel@nongnu.org; Mon, 01 Sep 2008 15:05:48 -0400 Received: from [199.232.76.173] (port=51993 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1KaEig-0000iw-Tt for qemu-devel@nongnu.org; Mon, 01 Sep 2008 15:05:46 -0400 Received: from wf-out-1314.google.com ([209.85.200.172]:13779) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1KaEig-0003Mj-9J for qemu-devel@nongnu.org; Mon, 01 Sep 2008 15:05:46 -0400 Received: by wf-out-1314.google.com with SMTP id 27so1982663wfd.4 for ; Mon, 01 Sep 2008 12:05:45 -0700 (PDT) Message-ID: Date: Mon, 1 Sep 2008 22:05:45 +0300 From: "Blue Swirl" Subject: Re: [Qemu-devel] sparc smul problem In-Reply-To: <20080901121035.R83237@stanley.csl.cornell.edu> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="----=_Part_17785_18400792.1220295945223" References: <20080901121035.R83237@stanley.csl.cornell.edu> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, Fabrice Bellard ------=_Part_17785_18400792.1220295945223 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Content-Disposition: inline On 9/1/08, Vince Weaver wrote: > Hello! > > I've been stuck on this all weekend, as I can't find where the actual > problem is. I might be completely missing it, but I've tried a lot of things > and can't make it work. > > On SPARC, the "smul" instruction multiplies two numbers, puts the result in > the result register but also puts the top 32-bits of the 64-bit result into > the "Y" register. > > As the attached code shows, the value of "Y" is wrong. Somehow after the > multiply, the top 32 bits of the product rae all zeros. I've played around > with the code generated by translate.c, and it looks like the shift and > other instructions all work properly, but the 64-bit multiply the result is > somehow being truncated. But I've looked at the generated code (on x86_64) > and it looks like it is doing the right thing. > > So anyway, I'll have to take a look at this again later, but in case anyone > else wants to look at it in case I am missing anything obvious. It looks like TCG on i386 host generates incorrect code for mulu2_i32, I think the op should be imul (unsigned) instead of mul. This patch fixes the problem. ------=_Part_17785_18400792.1220295945223 Content-Type: plain/text; name=fix_tcg_i386_mulu2.diff Content-Transfer-Encoding: base64 X-Attachment-Id: f_fklgmzlf Content-Disposition: attachment; filename=fix_tcg_i386_mulu2.diff SW5kZXg6IHFlbXUvdGNnL2kzODYvdGNnLXRhcmdldC5jCj09PT09PT09PT09PT09PT09PT09PT09 PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT0KLS0tIHFlbXUub3Jp Zy90Y2cvaTM4Ni90Y2ctdGFyZ2V0LmMJMjAwOC0wOS0wMSAxOTowMjoyNy4wMDAwMDAwMDAgKzAw MDAKKysrIHFlbXUvdGNnL2kzODYvdGNnLXRhcmdldC5jCTIwMDgtMDktMDEgMTk6MDI6MzEuMDAw MDAwMDAwICswMDAwCkBAIC05NjEsNyArOTYxLDcgQEAKICAgICAgICAgfQogICAgICAgICBicmVh azsKICAgICBjYXNlIElOREVYX29wX211bHUyX2kzMjoKLSAgICAgICAgdGNnX291dF9tb2RybShz LCAweGY3LCA0LCBhcmdzWzNdKTsKKyAgICAgICAgdGNnX291dF9tb2RybShzLCAweGY3LCA1LCBh cmdzWzNdKTsKICAgICAgICAgYnJlYWs7CiAgICAgY2FzZSBJTkRFWF9vcF9kaXYyX2kzMjoKICAg ICAgICAgdGNnX291dF9tb2RybShzLCAweGY3LCA3LCBhcmdzWzRdKTsK ------=_Part_17785_18400792.1220295945223--