From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1KaZAA-0001VP-Oa for qemu-devel@nongnu.org; Tue, 02 Sep 2008 12:55:30 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1KaZA9-0001UX-4Y for qemu-devel@nongnu.org; Tue, 02 Sep 2008 12:55:30 -0400 Received: from [199.232.76.173] (port=45557 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1KaZA9-0001UP-00 for qemu-devel@nongnu.org; Tue, 02 Sep 2008 12:55:29 -0400 Received: from wf-out-1314.google.com ([209.85.200.169]:24671) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1KaZA8-0007Jg-Cj for qemu-devel@nongnu.org; Tue, 02 Sep 2008 12:55:28 -0400 Received: by wf-out-1314.google.com with SMTP id 27so2399758wfd.4 for ; Tue, 02 Sep 2008 09:55:25 -0700 (PDT) Message-ID: Date: Tue, 2 Sep 2008 19:55:25 +0300 From: "Blue Swirl" Subject: Re: [Qemu-devel] [5123] Fix y register loads and stores In-Reply-To: <20080901190455.M84611@stanley.csl.cornell.edu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Content-Disposition: inline References: <20080901173717.J84348@stanley.csl.cornell.edu> <20080901182340.H84348@stanley.csl.cornell.edu> <20080901190455.M84611@stanley.csl.cornell.edu> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org On 9/2/08, Vince Weaver wrote: > > > > So something is wrong with the sign extension. Unfortunately I won't have > time to look into this more until tomorrow, but I wanted to just get this > out there. > > > > I did have time to look at it in the end. > > Here's a patch that fixes my test case. I'll have to look at the sparcv9 > manual closer to make sure it's the right thing to do. > > Vince > > --- ./target-sparc/translate.c.orig 2008-09-01 > 19:03:10.000000000 -0400 > +++ ./target-sparc/translate.c 2008-09-01 19:02:54.000000000 -0400 > @@ -793,8 +793,8 @@ > r_temp = tcg_temp_new(TCG_TYPE_I64); > r_temp2 = tcg_temp_new(TCG_TYPE_I64); > > - tcg_gen_ext_tl_i64(r_temp, src2); > - tcg_gen_ext_tl_i64(r_temp2, src1); > + tcg_gen_ext_i32_i64(r_temp, src2); > + tcg_gen_ext_i32_i64(r_temp2, src1); > > tcg_gen_mul_i64(r_temp2, r_temp, r_temp2); > > tcg_gen_shri_i64(r_temp, r_temp2, 32); Thanks, applied to both umul and smul.