From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1KeqUH-00045R-HV for qemu-devel@nongnu.org; Sun, 14 Sep 2008 08:13:57 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1KeqUG-00045B-3i for qemu-devel@nongnu.org; Sun, 14 Sep 2008 08:13:57 -0400 Received: from [199.232.76.173] (port=41879 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1KeqUG-000458-1R for qemu-devel@nongnu.org; Sun, 14 Sep 2008 08:13:56 -0400 Received: from wf-out-1314.google.com ([209.85.200.174]:38972) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1KeqUF-00021m-Nn for qemu-devel@nongnu.org; Sun, 14 Sep 2008 08:13:56 -0400 Received: by wf-out-1314.google.com with SMTP id 27so1576268wfd.4 for ; Sun, 14 Sep 2008 05:13:54 -0700 (PDT) Message-ID: Date: Sun, 14 Sep 2008 15:13:54 +0300 From: "Blue Swirl" Subject: Re: [Qemu-devel] [PATCH 2/2] ppc: Convert op_andi to TCG In-Reply-To: <200809141303.27871.paul@codesourcery.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Content-Disposition: inline References: <0485E6FE-5D41-4E23-88F7-514FA3A25C4C@web.de> <200809141303.27871.paul@codesourcery.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paul Brook Cc: =?UTF-8?Q?Andreas_F=C3=A4rber?= , qemu-devel@nongnu.org, Aurelien Jarno On 9/14/08, Paul Brook wrote: > > > > > tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); > > > > > - gen_op_andi_T0(UIMM(ctx->opcode)); > > > > > + tcg_gen_andi_tl(cpu_T[0], cpu_T[0], UIMM(ctx->opcode)); > > > > > tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); > > > > > gen_set_Rc0(ctx); > > > > > } > > > > > > > > Small comment: this would be more optimally: > > > > tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], > > > > cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode)); > > > > > > > > The same applies to andis. > > > > > > Careful there, iirc this cannot be done before gen_set_Rc0 is converted! > > > > I didn't mean to remove gen_set_Rc0, the comment only applied to the > > mov+andi+mov sequence. > > > set_Rc0 relies on T0 being set correctly be the preceding sequence. I see. I just read the patch, not the affected code, sorry for the noise.