Re: [Qemu-devel] [PATCH] SH4: Privilege check for instructions

["Blue Swirl" <blauwirbel@gmail.com>]

On 9/15/08, Shin-ichiro KAWASAKI <kawasaki@juno.dti.ne.jp> wrote:
> Blue Swirl wrote:
>
> > On 9/14/08, Shin-ichiro KAWASAKI <kawasaki@juno.dti.ne.jp> wrote:
> >
> > > Thank you for the comment!
> > >
> > >  Blue Swirl wrote:
> > >
> > >
> > > > On 9/14/08, Shin-ichiro KAWASAKI <kawasaki@juno.dti.ne.jp> wrote:
> > > >
> > > >
> > > > > This patch adds check for all SH4 instructions which are
> > > > >  executed only in privileged mode.
> > > > >
> > > > >
> > > > The checks get the privileged mode status from translation context. In
> > > > theory, the same TB code block could be used in unprivileged and
> > > > privileged mode, so the status that was true at translation time may
> > > > no longer be correct at execution time. Of course normally kernel code
> > > > is not visible or executable to user processes.
> > > >
> > > >
> > >  As you say, this patch has the restriction that you pointed out : the
> > >  generated TB cannot used for both unprivileged and privileged.
> > >
> >
> > Qemu will happily use the same TB for both modes, if the TB flags
> > match (cpu-exec.c):
> >
> >    if (unlikely(!tb || tb->pc != pc || tb->cs_base != cs_base ||
> >                 tb->flags != flags)) {
> >        tb = tb_find_slow(pc, cs_base, flags);
> >    }
> >
>
>  Thanks!  I have not understood this point.  You mean,
>  the main problem is that the one TB can be reused for both modes, and to
> check if new translation for the TB is necessary or not,
>  flags should contain enough information taken from CPU status.

Right.

> > >  I guess the codes generated by tcg_gen_qemu_st/ld() have the same
> > >  restriction, because those tcg_gen functions take the argument QEMU
> memory
> > >  index flags, which is decided at translation time.  If it is true, the
> > >  restriction might be allowed for privilege check.
> > >
> >
> > The loads and stores have the same problem, the generated code assumes
> > that the privilege mode stays the same as what it was during
> > translation.
> >
>
>  And the other problem is that loads/stores instructions (and privilege
>  instructions), cannot follow some CPU status changes within one TB.
>  This problem will be left considering the trade off with performance.

The loads/stores will use the ctx->memidx, but that's fine as long as
ctx->memidx is accurate. To ensure this, the supervisor/user bits of
the CPU status may not change during the TB, all instructions that
write to those bits must end the TB. Maybe the other instructions are
fine, but how about  'rte'?