From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1KvFTr-0006MA-Ax for qemu-devel@nongnu.org; Wed, 29 Oct 2008 14:09:19 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1KvFTp-0006L7-Je for qemu-devel@nongnu.org; Wed, 29 Oct 2008 14:09:18 -0400 Received: from [199.232.76.173] (port=60482 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1KvFTp-0006Kr-DD for qemu-devel@nongnu.org; Wed, 29 Oct 2008 14:09:17 -0400 Received: from rn-out-0910.google.com ([64.233.170.186]:25901) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1KvFTp-0000G2-5P for qemu-devel@nongnu.org; Wed, 29 Oct 2008 14:09:17 -0400 Received: by rn-out-0910.google.com with SMTP id m61so85533rnd.8 for ; Wed, 29 Oct 2008 11:09:15 -0700 (PDT) Message-ID: Date: Wed, 29 Oct 2008 20:09:15 +0200 From: "Blue Swirl" In-Reply-To: <200810282058.m9SKwVfH004300@smtp12.dti.ne.jp> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Content-Disposition: inline References: <20080923013136.490117fd.yoshii.takashi@gmail.com> <200810261517.m9QFHcH5026102@smtp12.dti.ne.jp> <200810282058.m9SKwVfH004300@smtp12.dti.ne.jp> Subject: [Qemu-devel] Re: [PATCH 2/3] take3 sh4: Add IRL(4bit encoded interrupt input) support. Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "takasi-y@ops.dti.ne.jp" Cc: qemu-devel@nongnu.org On 10/28/08, takasi-y@ops.dti.ne.jp wrote: > > Isn't it possible to use existing qemu_irq for the signals instead? On > > Sparc32, I have used qemu_irq for interrupt lines, reset signals and a > > terminal count pulse, one version used it for DMA request. > > I have re-written them using qemu_irq. > This use qemu_irq as multi-level signal. I mean LEVEL as in > qemu_set_irq(irq, LEVEL) is {0...15} but {0,1}. If an irq is active at some level, and another irq at some other level arrives, doesn't the first one get lost? Maybe SH has edge-triggered irqs and this is OK, I don't know. Sparc32 has similar 15 level interrupt system with priorities. I've used a separate qemu_irq for each of these, but perhaps your way could work if I used a bitmap.