From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Kz7sa-0006Mz-CR for qemu-devel@nongnu.org; Sun, 09 Nov 2008 05:50:52 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Kz7sY-0006Mn-L3 for qemu-devel@nongnu.org; Sun, 09 Nov 2008 05:50:51 -0500 Received: from [199.232.76.173] (port=53508 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Kz7sY-0006Mk-Eg for qemu-devel@nongnu.org; Sun, 09 Nov 2008 05:50:50 -0500 Received: from wf-out-1314.google.com ([209.85.200.175]:46260) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1Kz7sX-0004nO-M6 for qemu-devel@nongnu.org; Sun, 09 Nov 2008 05:50:50 -0500 Received: by wf-out-1314.google.com with SMTP id 27so2051747wfd.4 for ; Sun, 09 Nov 2008 02:50:46 -0800 (PST) Message-ID: Date: Sun, 9 Nov 2008 12:50:46 +0200 From: "Blue Swirl" Subject: Re: [Qemu-devel] [RFC] TCG new op: setcond In-Reply-To: <761ea48b0811050811l18152234jfc3046f2a502fecf@mail.gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Content-Disposition: inline References: <761ea48b0811040215l3fa16cd6j41e7ee750602e6ea@mail.gmail.com> <49105B1D.6080901@redhat.com> <761ea48b0811050811l18152234jfc3046f2a502fecf@mail.gmail.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org On 11/5/08, Laurent Desnogues wrote: > Hello, > > Here is an updated patch for setcond. > > Changes since the previous patch: > > - support TCG i386 for 32 and 64 bit variants > - support TCG x86_64 support for 32 and 64 bit variants > - fix for x86_64 prefix output > - fix for input/output overlap > - use setcond for Alpha cmp instructions > - add setcondi > > Digging into x86 is certainly not a pleasant experience for me, > especially as I have no experience on it. So this patch may > contain bugs and overlooks; note however my changes were > tested on x86_64 and i386 platforms with test programs for > Alpha and ARM. > > What remains to be done: > > > - document setcond in tcg/README > > - implement it in all backends (ARM, PPC, PPC64, SPARC) There is no equivalent instruction for Sparc32 (V8), it should be implemented otherwise. Though currently we assume that V9 is always available. Sparc64 (V9) has a conditional move instruction (MOVcc). The manual suggests a three-instruction sequence (cmp, mov, movcc) to implement a setcond-type operation. For setcondi where the immediate value is zero, MOVR may be used to skip the comparison (mov, movrcc). > - use it at least once in every frontend (cris, i386, m68k, MIPS, > PPC, sh4, SPARC) Candidate brconds to be replaced by setcond in target-sparc/translate are: all of gen_cc_*, gen_op_mulscc, gen_op_div_cc and gen_cond_reg. Especially gen_cond_reg should benefit. > Also there's a choice to be done between return 1 if the test > succeeds or -1. '1' would be much more useful than '-1' for Sparc target, because it can be shifted to form PSR_xxx values that can be or'ed to the condition codes. All of the above candidates except gen_cond_reg would need additional masking to remove the other bits than the zeroth.