From: "Blue Swirl" <blauwirbel@gmail.com>
To: qemu-devel@nongnu.org
Cc: Hollis Blanchard <hollisb@us.ibm.com>
Subject: Re: [Qemu-devel] [PATCH] IBM PowerPC 4xx 32-bit PCI controller emulation
Date: Mon, 1 Dec 2008 20:15:48 +0200 [thread overview]
Message-ID: <f43fc5580812011015y4ce64820taa77a075db730f80@mail.gmail.com> (raw)
In-Reply-To: <1227727332-17939-1-git-send-email-hollisb@us.ibm.com>
On 11/26/08, Hollis Blanchard <hollisb@us.ibm.com> wrote:
> This PCI controller can be found on a number of 4xx SoCs, including the 440EP.
>
> Signed-off-by: Hollis Blanchard <hollisb@us.ibm.com>
> ---
> This isn't yet used by the ppc405 boards qemu emulates, but it could be if
> someone has a 405 firmware/kernel they're able to test with.
The device can't be tested unless it's used by some board.
> +#if 0
> + printf("### %s: devfn %x irq %d -> %d\n", __func__,
> + pci_dev->devfn, irq_num, slot+1);
> +#endif
You could introduce a DPRINTF macro, like for example in slavio_intctl.c.
> + /* Board IRQs 2-5 are connected to UIC IRQs 28-25 */
> + /* XXX Needs some abstracting for boards other than Bamboo. */
> + qemu_set_irq(pic[30-irq_num], level);
> +}
The IRQs should be set up at the board level and then passed to the device.
> + /* XXX register_savevm() */
And register_reset?
next prev parent reply other threads:[~2008-12-01 18:15 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-11-26 19:22 [Qemu-devel] [PATCH] IBM PowerPC 4xx 32-bit PCI controller emulation Hollis Blanchard
2008-12-01 16:13 ` [Qemu-devel] " Hollis Blanchard
2008-12-01 18:15 ` Blue Swirl [this message]
2008-12-01 19:17 ` [Qemu-devel] " Hollis Blanchard
2008-12-01 19:59 ` Hollis Blanchard
2008-12-01 20:51 ` Blue Swirl
2008-12-02 20:02 ` [Qemu-devel] [PATCH 1/1] " Hollis Blanchard
2008-12-02 20:22 ` Anthony Liguori
2008-12-02 20:43 ` Hollis Blanchard
2008-12-02 22:13 ` Aurelien Jarno
2008-12-02 21:30 ` [Qemu-devel] [PATCH] [v3] " Hollis Blanchard
2008-12-02 22:01 ` Anthony Liguori
2008-12-02 23:53 ` Aurelien Jarno
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