From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1L7DJI-000470-UA for qemu-devel@nongnu.org; Mon, 01 Dec 2008 13:15:52 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1L7DJH-00046K-DX for qemu-devel@nongnu.org; Mon, 01 Dec 2008 13:15:52 -0500 Received: from [199.232.76.173] (port=56256 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1L7DJH-00046F-2e for qemu-devel@nongnu.org; Mon, 01 Dec 2008 13:15:51 -0500 Received: from mail-qy0-f20.google.com ([209.85.221.20]:60965) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1L7DJG-0005uI-NH for qemu-devel@nongnu.org; Mon, 01 Dec 2008 13:15:50 -0500 Received: by qyk13 with SMTP id 13so4349157qyk.10 for ; Mon, 01 Dec 2008 10:15:49 -0800 (PST) Message-ID: Date: Mon, 1 Dec 2008 20:15:48 +0200 From: "Blue Swirl" Subject: Re: [Qemu-devel] [PATCH] IBM PowerPC 4xx 32-bit PCI controller emulation In-Reply-To: <1227727332-17939-1-git-send-email-hollisb@us.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Content-Disposition: inline References: <1227727332-17939-1-git-send-email-hollisb@us.ibm.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Hollis Blanchard On 11/26/08, Hollis Blanchard wrote: > This PCI controller can be found on a number of 4xx SoCs, including the 440EP. > > Signed-off-by: Hollis Blanchard > --- > This isn't yet used by the ppc405 boards qemu emulates, but it could be if > someone has a 405 firmware/kernel they're able to test with. The device can't be tested unless it's used by some board. > +#if 0 > + printf("### %s: devfn %x irq %d -> %d\n", __func__, > + pci_dev->devfn, irq_num, slot+1); > +#endif You could introduce a DPRINTF macro, like for example in slavio_intctl.c. > + /* Board IRQs 2-5 are connected to UIC IRQs 28-25 */ > + /* XXX Needs some abstracting for boards other than Bamboo. */ > + qemu_set_irq(pic[30-irq_num], level); > +} The IRQs should be set up at the board level and then passed to the device. > + /* XXX register_savevm() */ And register_reset?