Index: qemu/hw/apic.c
===================================================================
--- qemu.orig/hw/apic.c	2008-12-07 14:58:07.000000000 +0000
+++ qemu/hw/apic.c	2008-12-07 14:58:12.000000000 +0000
@@ -614,7 +614,7 @@
         return 0;
     s = env->apic_state;
 
-    index = (addr >> 4) & 0xff;
+    index = addr >> 4;
     switch(index) {
     case 0x02: /* id */
         val = s->id << 24;
@@ -698,7 +698,7 @@
     printf("APIC write: %08x = %08x\n", (uint32_t)addr, val);
 #endif
 
-    index = (addr >> 4) & 0xff;
+    index = addr >> 4;
     switch(index) {
     case 0x02:
         s->id = (val >> 24);
Index: qemu/hw/cirrus_vga.c
===================================================================
--- qemu.orig/hw/cirrus_vga.c	2008-12-07 14:58:08.000000000 +0000
+++ qemu/hw/cirrus_vga.c	2008-12-07 14:58:12.000000000 +0000
@@ -2017,8 +2017,6 @@
 	return vga_mem_readb(s, addr);
     }
 
-    addr &= 0x1ffff;
-
     if (addr < 0x10000) {
 	/* XXX handle bitblt */
 	/* video memory */
@@ -2093,8 +2091,6 @@
         return;
     }
 
-    addr &= 0x1ffff;
-
     if (addr < 0x10000) {
 	if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
 	    /* bitblt */
@@ -2975,8 +2971,6 @@
 {
     CirrusVGAState *s = (CirrusVGAState *) opaque;
 
-    addr &= CIRRUS_PNPMMIO_SIZE - 1;
-
     if (addr >= 0x100) {
         return cirrus_mmio_blt_read(s, addr - 0x100);
     } else {
@@ -3019,8 +3013,6 @@
 {
     CirrusVGAState *s = (CirrusVGAState *) opaque;
 
-    addr &= CIRRUS_PNPMMIO_SIZE - 1;
-
     if (addr >= 0x100) {
 	cirrus_mmio_blt_write(s, addr - 0x100, val);
     } else {
Index: qemu/hw/cuda.c
===================================================================
--- qemu.orig/hw/cuda.c	2008-12-07 14:58:08.000000000 +0000
+++ qemu/hw/cuda.c	2008-12-07 14:58:12.000000000 +0000
@@ -250,7 +250,7 @@
     CUDAState *s = opaque;
     uint32_t val;
 
-    addr = (addr >> 9) & 0xf;
+    addr = addr >> 9;
     switch(addr) {
     case 0:
         val = s->b;
@@ -322,7 +322,7 @@
 {
     CUDAState *s = opaque;
 
-    addr = (addr >> 9) & 0xf;
+    addr = addr >> 9;
 #ifdef DEBUG_CUDA
     printf("cuda: write: reg=0x%x val=%02x\n", addr, val);
 #endif
Index: qemu/hw/e1000.c
===================================================================
--- qemu.orig/hw/e1000.c	2008-12-07 14:58:09.000000000 +0000
+++ qemu/hw/e1000.c	2008-12-07 14:58:12.000000000 +0000
@@ -785,7 +785,7 @@
 e1000_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 {
     E1000State *s = opaque;
-    unsigned int index = (addr & 0x1ffff) >> 2;
+    unsigned int index = addr >> 2;
 
 #ifdef TARGET_WORDS_BIGENDIAN
     val = bswap32(val);
@@ -819,7 +819,7 @@
 e1000_mmio_readl(void *opaque, target_phys_addr_t addr)
 {
     E1000State *s = opaque;
-    unsigned int index = (addr & 0x1ffff) >> 2;
+    unsigned int index = addr >> 2;
 
     if (index < NREADOPS && macreg_readops[index])
     {
Index: qemu/hw/etraxfs_ser.c
===================================================================
--- qemu.orig/hw/etraxfs_ser.c	2008-12-07 14:58:08.000000000 +0000
+++ qemu/hw/etraxfs_ser.c	2008-12-07 14:58:12.000000000 +0000
@@ -97,7 +97,7 @@
 	D(CPUState *env = s->env);
 	uint32_t r = 0;
 
-	switch (addr & 0xfff)
+	switch (addr)
 	{
 		case RW_TR_CTRL:
 			r = s->rw_tr_ctrl;
@@ -150,7 +150,7 @@
 	unsigned char ch = value;
 	D(CPUState *env = s->env);
 
-	switch (addr & 0xfff)
+	switch (addr)
 	{
 		case RW_TR_CTRL:
 			D(printf("rw_tr_ctrl=%x\n", value));
Index: qemu/hw/g364fb.c
===================================================================
--- qemu.orig/hw/g364fb.c	2008-12-07 14:58:08.000000000 +0000
+++ qemu/hw/g364fb.c	2008-12-07 14:58:12.000000000 +0000
@@ -193,8 +193,6 @@
     //G364State *s = opaque;
     uint32_t val;
 
-    addr &= 0xffff;
-
     switch (addr) {
         default:
 #ifdef DEBUG_G364
@@ -233,8 +231,6 @@
 {
     G364State *s = opaque;
 
-    addr &= 0xffff;
-
 #ifdef DEBUG_G364
     printf("g364fb/ctrl: write 0x%02x at [" TARGET_FMT_lx "]\n", val, addr);
 #endif
Index: qemu/hw/gt64xxx.c
===================================================================
--- qemu.orig/hw/gt64xxx.c	2008-12-07 14:58:07.000000000 +0000
+++ qemu/hw/gt64xxx.c	2008-12-07 14:58:12.000000000 +0000
@@ -312,7 +312,7 @@
     if (!(s->regs[GT_CPU] & 0x00001000))
         val = bswap32(val);
 
-    saddr = (addr & 0xfff) >> 2;
+    saddr = addr >> 2;
     switch (saddr) {
 
     /* CPU Configuration */
@@ -589,7 +589,7 @@
     uint32_t val;
     uint32_t saddr;
 
-    saddr = (addr & 0xfff) >> 2;
+    saddr = addr >> 2;
     switch (saddr) {
 
     /* CPU Configuration */
Index: qemu/hw/heathrow_pic.c
===================================================================
--- qemu.orig/hw/heathrow_pic.c	2008-12-07 14:58:06.000000000 +0000
+++ qemu/hw/heathrow_pic.c	2008-12-07 14:58:12.000000000 +0000
@@ -63,7 +63,7 @@
 #ifdef TARGET_WORDS_BIGENDIAN
     value = bswap32(value);
 #endif
-    n = ((addr & 0xfff) - 0x10) >> 4;
+    n = (addr - 0x10) >> 4;
 #ifdef DEBUG
     printf("pic_writel: " PADDRX " %u: %08x\n", addr, n, value);
 #endif
@@ -93,7 +93,7 @@
     unsigned int n;
     uint32_t value;
 
-    n = ((addr & 0xfff) - 0x10) >> 4;
+    n = (addr - 0x10) >> 4;
     if (n >= 2) {
         value = 0;
     } else {
Index: qemu/hw/ide.c
===================================================================
--- qemu.orig/hw/ide.c	2008-12-07 14:58:07.000000000 +0000
+++ qemu/hw/ide.c	2008-12-07 14:58:12.000000000 +0000
@@ -3360,7 +3360,7 @@
 static void pmac_ide_writel (void *opaque,
                              target_phys_addr_t addr, uint32_t val)
 {
-    addr = (addr & 0xFFF) >> 4;
+    addr = addr >> 4;
 #ifdef TARGET_WORDS_BIGENDIAN
     val = bswap32(val);
 #endif
@@ -3373,7 +3373,7 @@
 {
     uint32_t retval;
 
-    addr = (addr & 0xFFF) >> 4;
+    addr = addr >> 4;
     if (addr == 0) {
         retval = ide_data_readl(opaque, 0);
     } else {
Index: qemu/hw/mcf_fec.c
===================================================================
--- qemu.orig/hw/mcf_fec.c	2008-12-07 14:58:07.000000000 +0000
+++ qemu/hw/mcf_fec.c	2008-12-07 14:58:12.000000000 +0000
@@ -216,7 +216,7 @@
 static uint32_t mcf_fec_read(void *opaque, target_phys_addr_t addr)
 {
     mcf_fec_state *s = (mcf_fec_state *)opaque;
-    switch (addr & 0x3ff) {
+    switch (addr) {
     case 0x004: return s->eir;
     case 0x008: return s->eimr;
     case 0x010: return s->rx_enabled ? (1 << 24) : 0; /* RDAR */
@@ -254,7 +254,7 @@
 static void mcf_fec_write(void *opaque, target_phys_addr_t addr, uint32_t value)
 {
     mcf_fec_state *s = (mcf_fec_state *)opaque;
-    switch (addr & 0x3ff) {
+    switch (addr) {
     case 0x004:
         s->eir &= ~value;
         break;
Index: qemu/hw/mcf_intc.c
===================================================================
--- qemu.orig/hw/mcf_intc.c	2008-12-07 14:58:08.000000000 +0000
+++ qemu/hw/mcf_intc.c	2008-12-07 14:58:12.000000000 +0000
@@ -45,7 +45,7 @@
 {
     int offset;
     mcf_intc_state *s = (mcf_intc_state *)opaque;
-    offset = addr & 0xff;
+    offset = addr;
     if (offset >= 0x40 && offset < 0x80) {
         return s->icr[offset - 0x40];
     }
@@ -77,7 +77,7 @@
 {
     int offset;
     mcf_intc_state *s = (mcf_intc_state *)opaque;
-    offset = addr & 0xff;
+    offset = addr;
     if (offset >= 0x40 && offset < 0x80) {
         int n = offset - 0x40;
         s->icr[n] = val;
Index: qemu/hw/mcf_uart.c
===================================================================
--- qemu.orig/hw/mcf_uart.c	2008-12-07 14:58:08.000000000 +0000
+++ qemu/hw/mcf_uart.c	2008-12-07 14:58:12.000000000 +0000
@@ -67,7 +67,7 @@
 uint32_t mcf_uart_read(void *opaque, target_phys_addr_t addr)
 {
     mcf_uart_state *s = (mcf_uart_state *)opaque;
-    switch (addr & 0x3f) {
+    switch (addr) {
     case 0x00:
         return s->mr[s->current_mr];
     case 0x04:
@@ -185,7 +185,7 @@
 void mcf_uart_write(void *opaque, target_phys_addr_t addr, uint32_t val)
 {
     mcf_uart_state *s = (mcf_uart_state *)opaque;
-    switch (addr & 0x3f) {
+    switch (addr) {
     case 0x00:
         s->mr[s->current_mr] = val;
         s->current_mr = 1;
Index: qemu/hw/mips_malta.c
===================================================================
--- qemu.orig/hw/mips_malta.c	2008-12-07 14:58:08.000000000 +0000
+++ qemu/hw/mips_malta.c	2008-12-07 14:58:12.000000000 +0000
@@ -225,7 +225,7 @@
     uint32_t val = 0;
     uint32_t saddr;
 
-    saddr = (addr & 0xfffff);
+    saddr = addr;
 
     switch (saddr) {
 
@@ -312,7 +312,7 @@
     MaltaFPGAState *s = opaque;
     uint32_t saddr;
 
-    saddr = (addr & 0xfffff);
+    saddr = addr;
 
     switch (saddr) {
 
Index: qemu/hw/mips_r4k.c
===================================================================
--- qemu.orig/hw/mips_r4k.c	2008-12-07 14:58:07.000000000 +0000
+++ qemu/hw/mips_r4k.c	2008-12-07 14:58:12.000000000 +0000
@@ -50,9 +50,9 @@
 static void mips_qemu_writel (void *opaque, target_phys_addr_t addr,
 			      uint32_t val)
 {
-    if ((addr & 0xffff) == 0 && val == 42)
+    if (addr == 0 && val == 42)
         qemu_system_reset_request ();
-    else if ((addr & 0xffff) == 4 && val == 42)
+    else if (addr == 4 && val == 42)
         qemu_system_shutdown_request ();
 }
 
Index: qemu/hw/mpcore.c
===================================================================
--- qemu.orig/hw/mpcore.c	2008-12-07 14:58:07.000000000 +0000
+++ qemu/hw/mpcore.c	2008-12-07 14:58:12.000000000 +0000
@@ -159,7 +159,7 @@
 {
     mpcore_priv_state *s = (mpcore_priv_state *)opaque;
     int id;
-    offset &= 0xfff;
+
     if (offset < 0x100) {
         /* SCU */
         switch (offset) {
@@ -205,7 +205,7 @@
 {
     mpcore_priv_state *s = (mpcore_priv_state *)opaque;
     int id;
-    offset &= 0xfff;
+
     if (offset < 0x100) {
         /* SCU */
         switch (offset) {
Index: qemu/hw/omap1.c
===================================================================
--- qemu.orig/hw/omap1.c	2008-12-07 14:58:08.000000000 +0000
+++ qemu/hw/omap1.c	2008-12-07 14:58:12.000000000 +0000
@@ -973,7 +973,7 @@
 static uint32_t omap_os_timer_read(void *opaque, target_phys_addr_t addr)
 {
     struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
-    int offset = addr & OMAP_MPUI_REG_MASK;
+    int offset = addr;
 
     switch (offset) {
     case 0x00:	/* TVR */
@@ -996,7 +996,7 @@
                 uint32_t value)
 {
     struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
-    int offset = addr & OMAP_MPUI_REG_MASK;
+    int offset = addr;
 
     switch (offset) {
     case 0x00:	/* TVR */
@@ -2576,7 +2576,7 @@
 static uint32_t omap_mpuio_read(void *opaque, target_phys_addr_t addr)
 {
     struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
-    int offset = addr & OMAP_MPUI_REG_MASK;
+    int offset = addr;
     uint16_t ret;
 
     switch (offset) {
@@ -2632,7 +2632,7 @@
                 uint32_t value)
 {
     struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
-    int offset = addr & OMAP_MPUI_REG_MASK;
+    int offset = addr;
     uint16_t diff;
     int ln;
 
@@ -3010,7 +3010,7 @@
 static uint32_t omap_uwire_read(void *opaque, target_phys_addr_t addr)
 {
     struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
-    int offset = addr & OMAP_MPUI_REG_MASK;
+    int offset = addr;
 
     switch (offset) {
     case 0x00:	/* RDR */
@@ -3040,7 +3040,7 @@
                 uint32_t value)
 {
     struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
-    int offset = addr & OMAP_MPUI_REG_MASK;
+    int offset = addr;
 
     switch (offset) {
     case 0x00:	/* TDR */
@@ -3151,7 +3151,7 @@
 static uint32_t omap_pwl_read(void *opaque, target_phys_addr_t addr)
 {
     struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
-    int offset = addr & OMAP_MPUI_REG_MASK;
+    int offset = addr;
 
     switch (offset) {
     case 0x00:	/* PWL_LEVEL */
@@ -3167,7 +3167,7 @@
                 uint32_t value)
 {
     struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
-    int offset = addr & OMAP_MPUI_REG_MASK;
+    int offset = addr;
 
     switch (offset) {
     case 0x00:	/* PWL_LEVEL */
@@ -3231,7 +3231,7 @@
 static uint32_t omap_pwt_read(void *opaque, target_phys_addr_t addr)
 {
     struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
-    int offset = addr & OMAP_MPUI_REG_MASK;
+    int offset = addr;
 
     switch (offset) {
     case 0x00:	/* FRC */
@@ -3249,7 +3249,7 @@
                 uint32_t value)
 {
     struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
-    int offset = addr & OMAP_MPUI_REG_MASK;
+    int offset = addr;
 
     switch (offset) {
     case 0x00:	/* FRC */
@@ -3367,7 +3367,7 @@
 static uint32_t omap_rtc_read(void *opaque, target_phys_addr_t addr)
 {
     struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
-    int offset = addr & OMAP_MPUI_REG_MASK;
+    int offset = addr;
     uint8_t i;
 
     switch (offset) {
@@ -3445,7 +3445,7 @@
                 uint32_t value)
 {
     struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
-    int offset = addr & OMAP_MPUI_REG_MASK;
+    int offset = addr;
     struct tm new_tm;
     time_t ti[2];
 
@@ -3953,7 +3953,7 @@
 static uint32_t omap_mcbsp_read(void *opaque, target_phys_addr_t addr)
 {
     struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
-    int offset = addr & OMAP_MPUI_REG_MASK;
+    int offset = addr;
     uint16_t ret;
 
     switch (offset) {
@@ -4047,7 +4047,7 @@
                 uint32_t value)
 {
     struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
-    int offset = addr & OMAP_MPUI_REG_MASK;
+    int offset = addr;
 
     switch (offset) {
     case 0x00:	/* DRR2 */
@@ -4185,7 +4185,7 @@
                 uint32_t value)
 {
     struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
-    int offset = addr & OMAP_MPUI_REG_MASK;
+    int offset = addr;
 
     if (offset == 0x04) {				/* DXR */
         if (((s->xcr[0] >> 5) & 7) < 3)			/* XWDLEN1 */
@@ -4361,7 +4361,7 @@
 static uint32_t omap_lpg_read(void *opaque, target_phys_addr_t addr)
 {
     struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
-    int offset = addr & OMAP_MPUI_REG_MASK;
+    int offset = addr;
 
     switch (offset) {
     case 0x00:	/* LCR */
@@ -4379,7 +4379,7 @@
                 uint32_t value)
 {
     struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
-    int offset = addr & OMAP_MPUI_REG_MASK;
+    int offset = addr;
 
     switch (offset) {
     case 0x00:	/* LCR */
Index: qemu/hw/openpic.c
===================================================================
--- qemu.orig/hw/openpic.c	2008-12-07 14:58:06.000000000 +0000
+++ qemu/hw/openpic.c	2008-12-07 14:58:12.000000000 +0000
@@ -920,7 +920,6 @@
 {
     openpic_t *opp = opaque;
 
-    addr &= 0x3FFFF;
     DPRINTF("%s: offset %08x val: %08x\n", __func__, (int)addr, val);
     if (addr < 0x1100) {
         /* Global registers */
@@ -942,7 +941,6 @@
     openpic_t *opp = opaque;
     uint32_t retval;
 
-    addr &= 0x3FFFF;
     DPRINTF("%s: offset %08x\n", __func__, (int)addr);
     if (addr < 0x1100) {
         /* Global registers */
Index: qemu/hw/pcnet.c
===================================================================
--- qemu.orig/hw/pcnet.c	2008-12-07 14:58:08.000000000 +0000
+++ qemu/hw/pcnet.c	2008-12-07 14:58:12.000000000 +0000
@@ -1802,7 +1802,6 @@
     if (addr & 0x10)
         pcnet_ioport_writew(d, addr & 0x0f, val);
     else {
-        addr &= 0x0f;
         pcnet_aprom_writeb(d, addr, val & 0xff);
         pcnet_aprom_writeb(d, addr+1, (val & 0xff00) >> 8);
     }
@@ -1815,7 +1814,6 @@
     if (addr & 0x10)
         val = pcnet_ioport_readw(d, addr & 0x0f);
     else {
-        addr &= 0x0f;
         val = pcnet_aprom_readb(d, addr+1);
         val <<= 8;
         val |= pcnet_aprom_readb(d, addr);
@@ -1837,7 +1835,6 @@
     if (addr & 0x10)
         pcnet_ioport_writel(d, addr & 0x0f, val);
     else {
-        addr &= 0x0f;
         pcnet_aprom_writeb(d, addr, val & 0xff);
         pcnet_aprom_writeb(d, addr+1, (val & 0xff00) >> 8);
         pcnet_aprom_writeb(d, addr+2, (val & 0xff0000) >> 16);
@@ -1852,7 +1849,6 @@
     if (addr & 0x10)
         val = pcnet_ioport_readl(d, addr & 0x0f);
     else {
-        addr &= 0x0f;
         val = pcnet_aprom_readb(d, addr+3);
         val <<= 8;
         val |= pcnet_aprom_readb(d, addr+2);
Index: qemu/hw/pl011.c
===================================================================
--- qemu.orig/hw/pl011.c	2008-12-07 14:58:07.000000000 +0000
+++ qemu/hw/pl011.c	2008-12-07 14:58:12.000000000 +0000
@@ -58,7 +58,7 @@
     pl011_state *s = (pl011_state *)opaque;
     uint32_t c;
 
-    if (offset >= 0xfe0 && offset < 0x1000) {
+    if (offset >= 0xfe0) {
         return pl011_id[s->type][(offset - 0xfe0) >> 2];
     }
     switch (offset >> 2) {
Index: qemu/hw/pl022.c
===================================================================
--- qemu.orig/hw/pl022.c	2008-12-07 14:58:07.000000000 +0000
+++ qemu/hw/pl022.c	2008-12-07 14:58:12.000000000 +0000
@@ -136,7 +136,7 @@
     pl022_state *s = (pl022_state *)opaque;
     int val;
 
-    if (offset >= 0xfe0 && offset < 0x1000) {
+    if (offset >= 0xfe0) {
         return pl022_id[(offset - 0xfe0) >> 2];
     }
     switch (offset) {
Index: qemu/hw/pl031.c
===================================================================
--- qemu.orig/hw/pl031.c	2008-12-07 14:58:08.000000000 +0000
+++ qemu/hw/pl031.c	2008-12-07 14:58:12.000000000 +0000
@@ -96,7 +96,7 @@
 {
     pl031_state *s = (pl031_state *)opaque;
 
-    if (offset >= 0xfe0  &&  offset < 0x1000)
+    if (offset >= 0xfe0)
         return pl031_id[(offset - 0xfe0) >> 2];
 
     switch (offset) {
Index: qemu/hw/pl050.c
===================================================================
--- qemu.orig/hw/pl050.c	2008-12-07 14:58:07.000000000 +0000
+++ qemu/hw/pl050.c	2008-12-07 14:58:12.000000000 +0000
@@ -46,7 +46,7 @@
 static uint32_t pl050_read(void *opaque, target_phys_addr_t offset)
 {
     pl050_state *s = (pl050_state *)opaque;
-    if (offset >= 0xfe0 && offset < 0x1000)
+    if (offset >= 0xfe0)
         return pl050_id[(offset - 0xfe0) >> 2];
 
     switch (offset >> 2) {
Index: qemu/hw/pl061.c
===================================================================
--- qemu.orig/hw/pl061.c	2008-12-07 14:58:07.000000000 +0000
+++ qemu/hw/pl061.c	2008-12-07 14:58:12.000000000 +0000
@@ -82,7 +82,7 @@
 {
     pl061_state *s = (pl061_state *)opaque;
 
-    if (offset >= 0xfd0 && offset < 0x1000) {
+    if (offset >= 0xfd0) {
         return pl061_id[(offset - 0xfd0) >> 2];
     }
     if (offset < 0x400) {
Index: qemu/hw/pl080.c
===================================================================
--- qemu.orig/hw/pl080.c	2008-12-07 14:58:08.000000000 +0000
+++ qemu/hw/pl080.c	2008-12-07 14:58:12.000000000 +0000
@@ -186,7 +186,7 @@
     uint32_t i;
     uint32_t mask;
 
-    if (offset >= 0xfe0 && offset < 0x1000) {
+    if (offset >= 0xfe0) {
         if (s->nchannels == 8) {
             return pl080_id[(offset - 0xfe0) >> 2];
         } else {
Index: qemu/hw/pl110.c
===================================================================
--- qemu.orig/hw/pl110.c	2008-12-07 14:58:07.000000000 +0000
+++ qemu/hw/pl110.c	2008-12-07 14:58:12.000000000 +0000
@@ -288,7 +288,7 @@
 {
     pl110_state *s = (pl110_state *)opaque;
 
-    if (offset >= 0xfe0 && offset < 0x1000) {
+    if (offset >= 0xfe0) {
         if (s->versatile)
             return pl110_versatile_id[(offset - 0xfe0) >> 2];
         else
Index: qemu/hw/pl181.c
===================================================================
--- qemu.orig/hw/pl181.c	2008-12-07 14:58:08.000000000 +0000
+++ qemu/hw/pl181.c	2008-12-07 14:58:12.000000000 +0000
@@ -260,7 +260,7 @@
     pl181_state *s = (pl181_state *)opaque;
     uint32_t tmp;
 
-    if (offset >= 0xfe0 && offset < 0x1000) {
+    if (offset >= 0xfe0) {
         return pl181_id[(offset - 0xfe0) >> 2];
     }
     switch (offset) {
Index: qemu/hw/pl190.c
===================================================================
--- qemu.orig/hw/pl190.c	2008-12-07 14:58:07.000000000 +0000
+++ qemu/hw/pl190.c	2008-12-07 14:58:12.000000000 +0000
@@ -91,7 +91,7 @@
     pl190_state *s = (pl190_state *)opaque;
     int i;
 
-    if (offset >= 0xfe0 && offset < 0x1000) {
+    if (offset >= 0xfe0) {
         return pl190_id[(offset - 0xfe0) >> 2];
     }
     if (offset >= 0x100 && offset < 0x140) {
Index: qemu/hw/ppc_prep.c
===================================================================
--- qemu.orig/hw/ppc_prep.c	2008-12-07 14:58:08.000000000 +0000
+++ qemu/hw/ppc_prep.c	2008-12-07 14:58:12.000000000 +0000
@@ -122,7 +122,7 @@
 {
     uint32_t retval = 0;
 
-    if ((addr & 0xf) == 0)
+    if (addr == 0)
         retval = pic_intack_read(isa_pic);
 //   printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
 
Index: qemu/hw/rc4030.c
===================================================================
--- qemu.orig/hw/rc4030.c	2008-12-07 14:58:08.000000000 +0000
+++ qemu/hw/rc4030.c	2008-12-07 14:58:12.000000000 +0000
@@ -83,7 +83,6 @@
     rc4030State *s = opaque;
     uint32_t val;
 
-    addr &= 0x3fff;
     switch (addr & ~0x3) {
     /* Global config register */
     case 0x0000:
@@ -228,7 +227,6 @@
 static void rc4030_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 {
     rc4030State *s = opaque;
-    addr &= 0x3fff;
 
 #ifdef DEBUG_RC4030
     printf("rc4030: write 0x%02x at " TARGET_FMT_lx "\n", val, addr);
@@ -446,7 +444,6 @@
     rc4030State *s = opaque;
     uint32_t val;
     uint32_t irq;
-    addr &= 0xfff;
 
     switch (addr) {
     case 0x00: {
@@ -500,7 +497,6 @@
 static void int_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
 {
     rc4030State *s = opaque;
-    addr &= 0xfff;
 
 #ifdef DEBUG_RC4030
     printf("rc4030: (interrupt controller) write 0x%02x at " TARGET_FMT_lx "\n", val, addr);
Index: qemu/hw/rtl8139.c
===================================================================
--- qemu.orig/hw/rtl8139.c	2008-12-07 14:58:07.000000000 +0000
+++ qemu/hw/rtl8139.c	2008-12-07 14:58:12.000000000 +0000
@@ -3030,39 +3030,39 @@
 
 static void rtl8139_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
 {
-    rtl8139_io_writeb(opaque, addr & 0xFF, val);
+    rtl8139_io_writeb(opaque, addr, val);
 }
 
 static void rtl8139_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
 {
-    rtl8139_io_writew(opaque, addr & 0xFF, val);
+    rtl8139_io_writew(opaque, addr, val);
 }
 
 static void rtl8139_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
 {
-    rtl8139_io_writel(opaque, addr & 0xFF, val);
+    rtl8139_io_writel(opaque, addr, val);
 }
 
 static uint32_t rtl8139_ioport_readb(void *opaque, uint32_t addr)
 {
-    return rtl8139_io_readb(opaque, addr & 0xFF);
+    return rtl8139_io_readb(opaque, addr);
 }
 
 static uint32_t rtl8139_ioport_readw(void *opaque, uint32_t addr)
 {
-    return rtl8139_io_readw(opaque, addr & 0xFF);
+    return rtl8139_io_readw(opaque, addr);
 }
 
 static uint32_t rtl8139_ioport_readl(void *opaque, uint32_t addr)
 {
-    return rtl8139_io_readl(opaque, addr & 0xFF);
+    return rtl8139_io_readl(opaque, addr);
 }
 
 /* */
 
 static void rtl8139_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
 {
-    rtl8139_io_writeb(opaque, addr & 0xFF, val);
+    rtl8139_io_writeb(opaque, addr, val);
 }
 
 static void rtl8139_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
@@ -3070,7 +3070,7 @@
 #ifdef TARGET_WORDS_BIGENDIAN
     val = bswap16(val);
 #endif
-    rtl8139_io_writew(opaque, addr & 0xFF, val);
+    rtl8139_io_writew(opaque, addr, val);
 }
 
 static void rtl8139_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
@@ -3078,17 +3078,17 @@
 #ifdef TARGET_WORDS_BIGENDIAN
     val = bswap32(val);
 #endif
-    rtl8139_io_writel(opaque, addr & 0xFF, val);
+    rtl8139_io_writel(opaque, addr, val);
 }
 
 static uint32_t rtl8139_mmio_readb(void *opaque, target_phys_addr_t addr)
 {
-    return rtl8139_io_readb(opaque, addr & 0xFF);
+    return rtl8139_io_readb(opaque, addr);
 }
 
 static uint32_t rtl8139_mmio_readw(void *opaque, target_phys_addr_t addr)
 {
-    uint32_t val = rtl8139_io_readw(opaque, addr & 0xFF);
+    uint32_t val = rtl8139_io_readw(opaque, addr);
 #ifdef TARGET_WORDS_BIGENDIAN
     val = bswap16(val);
 #endif
@@ -3097,7 +3097,7 @@
 
 static uint32_t rtl8139_mmio_readl(void *opaque, target_phys_addr_t addr)
 {
-    uint32_t val = rtl8139_io_readl(opaque, addr & 0xFF);
+    uint32_t val = rtl8139_io_readl(opaque, addr);
 #ifdef TARGET_WORDS_BIGENDIAN
     val = bswap32(val);
 #endif
Index: qemu/hw/sm501.c
===================================================================
--- qemu.orig/hw/sm501.c	2008-12-07 14:58:08.000000000 +0000
+++ qemu/hw/sm501.c	2008-12-07 14:58:12.000000000 +0000
@@ -850,7 +850,6 @@
     /* TODO : consider BYTE/WORD access */
     /* TODO : consider endian */
 
-    assert(0 <= addr && addr < 0x400 * 3);
     return *(uint32_t*)&s->dc_palette[addr];
 }
 
@@ -864,7 +863,6 @@
     /* TODO : consider BYTE/WORD access */
     /* TODO : consider endian */
 
-    assert(0 <= addr && addr < 0x400 * 3);
     *(uint32_t*)&s->dc_palette[addr] = value;
 }
 
Index: qemu/hw/vga.c
===================================================================
--- qemu.orig/hw/vga.c	2008-12-07 14:58:08.000000000 +0000
+++ qemu/hw/vga.c	2008-12-07 14:58:12.000000000 +0000
@@ -713,7 +713,7 @@
 
     /* convert to VGA memory offset */
     memory_map_mode = (s->gr[6] >> 2) & 3;
-    addr &= 0x1ffff;
+
     switch(memory_map_mode) {
     case 0:
         break;
@@ -803,7 +803,7 @@
 #endif
     /* convert to VGA memory offset */
     memory_map_mode = (s->gr[6] >> 2) & 3;
-    addr &= 0x1ffff;
+
     switch(memory_map_mode) {
     case 0:
         break;
