Re: [Qemu-devel] [PATCH] PPC: Use correct values for 970 interrupts and hreset

[Blue Swirl <blauwirbel@gmail.com>]

On 2/28/09, Alexander Graf <alex@csgraf.de> wrote:
>
>  On 28.02.2009, at 16:21, Blue Swirl wrote:
>
>
> > On 2/28/09, Alexander Graf <agraf@suse.de> wrote:
> >
> > > The 970 doesn't set exception prefix values by default. According to
> > > the ISA it just jumps to real mode with nip=vector.
> > >
> > > Because of that the current hreset_vector is rendered invalid. Before,
> > > it would go to excp_prefix (ROM base) + 0x100 (reset vector) and get
> > > into the firmware.
> > >
> > > But with the corrected excp_prefix, we now have to jump to the real
> > > entry point, which is at 0xFFFFFFFC.
> > >
> >
> > I don't think this is correct. 970FX uses HIOR to specify the
> > exception vector base, please see "IBM PowerPC 970FX RISC
> > Microprocessor", page 273.
> >
>
>  Oh I think I know what you're saying:
>
>  The Hardware Interrupt Offset register, HIOR should be scanned (the HIOR is
> on the mode ring) to the
>  system’s starting address during initialization. Subsequently HIOR should
> be set to zero.
>
>  That basically means, HIOR is 0xfff00000 on bootup, but magically becomes 0
> at - eh - a random point in time? Or should the firmware set it? How is this
> implemented on a G5 that doesn't know LPAR features, like Apple's G5?

Firmware should clear it. Maybe their BIOS sets all unknown SPRs to 0?