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Date: Sat, 28 Feb 2009 17:49:34 +0200
Message-ID: <f43fc5580902280749w7fe1a393ka9c8e54f68d7b9b2@mail.gmail.com>
Subject: Re: [Qemu-devel] [PATCH] PPC: Use correct values for 970 interrupts
	and hreset
From: Blue Swirl <blauwirbel@gmail.com>
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To: Alexander Graf <alex@csgraf.de>
Cc: qemu-devel@nongnu.org

On 2/28/09, Alexander Graf <alex@csgraf.de> wrote:
>
>  On 28.02.2009, at 16:21, Blue Swirl wrote:
>
>
> > On 2/28/09, Alexander Graf <agraf@suse.de> wrote:
> >
> > > The 970 doesn't set exception prefix values by default. According to
> > > the ISA it just jumps to real mode with nip=3Dvector.
> > >
> > > Because of that the current hreset_vector is rendered invalid. Before=
,
> > > it would go to excp_prefix (ROM base) + 0x100 (reset vector) and get
> > > into the firmware.
> > >
> > > But with the corrected excp_prefix, we now have to jump to the real
> > > entry point, which is at 0xFFFFFFFC.
> > >
> >
> > I don't think this is correct. 970FX uses HIOR to specify the
> > exception vector base, please see "IBM PowerPC 970FX RISC
> > Microprocessor", page 273.
> >
>
>  Oh I think I know what you're saying:
>
>  The Hardware Interrupt Offset register, HIOR should be scanned (the HIOR=
 is
> on the mode ring) to the
>  system=E2=80=99s starting address during initialization. Subsequently HI=
OR should
> be set to zero.
>
>  That basically means, HIOR is 0xfff00000 on bootup, but magically become=
s 0
> at - eh - a random point in time? Or should the firmware set it? How is t=
his
> implemented on a G5 that doesn't know LPAR features, like Apple's G5?

Firmware should clear it. Maybe their BIOS sets all unknown SPRs to 0?