From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LdRaK-0007uQ-A7 for qemu-devel@nongnu.org; Sat, 28 Feb 2009 10:58:40 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LdRaI-0007sx-OB for qemu-devel@nongnu.org; Sat, 28 Feb 2009 10:58:39 -0500 Received: from [199.232.76.173] (port=44774 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LdRaI-0007so-HI for qemu-devel@nongnu.org; Sat, 28 Feb 2009 10:58:38 -0500 Received: from mail-bw0-f171.google.com ([209.85.218.171]:63021) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1LdRaH-0006No-T2 for qemu-devel@nongnu.org; Sat, 28 Feb 2009 10:58:38 -0500 Received: by bwz19 with SMTP id 19so1307859bwz.34 for ; Sat, 28 Feb 2009 07:58:36 -0800 (PST) MIME-Version: 1.0 In-Reply-To: References: <1235833386-30272-1-git-send-email-agraf@suse.de> Date: Sat, 28 Feb 2009 17:58:35 +0200 Message-ID: Subject: Re: [Qemu-devel] [PATCH] Make the ELF loader aware of backwards compatibility From: Blue Swirl Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Alexander Graf On 2/28/09, Andreas F=C3=A4rber wrote: > > Am 28.02.2009 um 16:30 schrieb Blue Swirl: > > > > On 2/28/09, Alexander Graf wrote: > > > > > Most 64 bit architectures I'm aware of support running 32 bit code > > > of the same architecture as well. > > > > > > > For Sparc64 this is only true for userland, kernel level code is not > > compatible at all. Sparc64 kernel can run Sparc64 and Sparc32 > > binaries, but a Sparc32 kernel will crash on Sparc64. > > > > Same for ppc. To install Linux, you need to type "install64" at the prom= pt, > the default "install" crashes on a G5. Not exactly. I guess it's possible to construct a dual PPC32/PPC64 kernel for 32 bit mode because even though the MMUs are not compatible, instruction sets are. But Sparc32 supervisor instructions do wildly different things on a Sparc64.