From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LiBRf-0003kg-Nb for qemu-devel@nongnu.org; Fri, 13 Mar 2009 13:45:19 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LiBRa-0003jV-Bv for qemu-devel@nongnu.org; Fri, 13 Mar 2009 13:45:18 -0400 Received: from [199.232.76.173] (port=46183 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LiBRa-0003jR-6g for qemu-devel@nongnu.org; Fri, 13 Mar 2009 13:45:14 -0400 Received: from mail-fx0-f161.google.com ([209.85.220.161]:45011) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1LiBRZ-0006zo-Ky for qemu-devel@nongnu.org; Fri, 13 Mar 2009 13:45:13 -0400 Received: by fxm5 with SMTP id 5so286093fxm.34 for ; Fri, 13 Mar 2009 10:45:12 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <1236954043-91856-10-git-send-email-gingold@adacore.com> References: <1236954043-91856-1-git-send-email-gingold@adacore.com> <1236954043-91856-2-git-send-email-gingold@adacore.com> <1236954043-91856-3-git-send-email-gingold@adacore.com> <1236954043-91856-4-git-send-email-gingold@adacore.com> <1236954043-91856-5-git-send-email-gingold@adacore.com> <1236954043-91856-6-git-send-email-gingold@adacore.com> <1236954043-91856-7-git-send-email-gingold@adacore.com> <1236954043-91856-8-git-send-email-gingold@adacore.com> <1236954043-91856-9-git-send-email-gingold@adacore.com> <1236954043-91856-10-git-send-email-gingold@adacore.com> Date: Fri, 13 Mar 2009 19:45:11 +0200 Message-ID: Subject: Re: [Qemu-devel] [PATCH 09/24] Split cpu_mmu_index into cpu_mmu_index_data and cpu_mmu_index_code. From: Blue Swirl Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org On 3/13/09, Tristan Gingold wrote: > This is required by alpha system emulation as PAL mode disable instruction > mmu but not data mmu. > This might also be required for other cpus that have a split I/D mmu enable. This is true for Sparc64 and PPC32/64 but I think normally both MMUs are enabled.